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512mb: x4, x8, x16 ddr sdram features pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d1.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 1 ?2000 micron technology, inc. all rights reserved. double data rate (ddr) sdram mt46v128m4 ? 32 meg x 4 x 4 banks MT46V64M8 ? 16 meg x 8 x 4 banks mt46v32m16 ? 8 meg x 16 x 4 banks features ?v dd = 2.5v 0.2v, v ddq = 2.5v 0.2v v dd = 2.6v 0.1v, v ddq = 2.6v 0.1v (ddr400) 1 ? bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two ? one per byte) ? internal, pipelined do uble-data-rate (ddr) architecture; two data acces ses per clock cycle ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? dll to align dq and dqs transitions with ck ? four internal banks for concurrent operation ? data mask (dm) for masking write data (x16 has two ? one per byte) ? programmable burst lengths: 2, 4, or 8 ?auto refresh ? 64ms, 8192-cycle ? longer-lead tsop for impro ved reliability (ocpl) ? 2.5v i/o (sstl_2 compatible) ? concurrent auto precharge option is supported ? t ras lockout supported ( t rap = t rcd) notes: 1. ddr400 devices operating at < ddr333 conditions can use v dd /v ddq = 2.5v + 0.2v. 2. available only on revision f. 3. available only on revision j. options marking ? configuration ? 128 meg x 4 (32 meg x 4 x 4 banks) 128m4 ? 64 meg x 8 (16 meg x 8 x 4 banks) 64m8 ? 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 ? plastic package ? 66-pin tsop tg ? 66-pin tsop (pb-free) p ? 60-ball fbga (10mm x 12.5mm) fn 2 ? 60-ball fbga (10mm x 12.5mm) (pb-free) bn 2 ? 60-ball fbga (8mm x 12.5mm) cv 3 ? 60-ball fbga (8mm x 12.5mm) (pb-free) cy 3 ? timing ? cycle time ? 5ns @ cl = 3 (ddr400) -5b ? 6ns @ cl = 2.5 (ddr333) (fbga only) -6 2 ? 6ns @ cl = 2.5 (ddr333) (tsop only) -6t 2 ? self refresh ? standard none ? low-power self refresh l ? temperature rating ? commercial (0c to +70c) none ? industrial (?40c to +85c) it ? revision ? x4, x8, x16 :f ? x4, x8, x16 :j table 1: key timing parameters cl = cas (read) latency; data-out window is min clock rate with 50% duty cycle at cl = 2, cl = 2.5, or cl = 3 speed grade clock rate (mhz) data-out window access window dqs?dq skew cl = 2 cl = 2.5 cl = 3 -5b 133 167 200 1.6ns 0.70ns 0.40ns -6 133 167 n/a 2.1ns 0.70ns 0.40ns 6t 133 167 n/a 2.0ns 0.70ns 0.45ns -75e/-75z 133 133 n/a 2.5ns 0.75ns 0.50ns -75 100 133 n/a 2.5ns 0.75ns 0.50ns
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d1.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 2 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram features notes: 1. the -5b device is backward compatible with all slower speed grades. the voltage range of -5b device operating at slower speed grades is v dd = v ddq = 2.5v 0.2v. figure 1: 512mb ddr sdram part numbers fbga part number system due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on micron?s web site: www.micron.com . table 2: addressing parameter 128 meg x 4 64 meg x 8 32 meg x 16 configuration 32 meg x 4 x 4 banks 16 meg x 8 x 4 banks 8 meg x 16 x 4 banks refresh count 8k 8k 8k row address 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) bank address 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) column address 4k (a0?a9, a11, a12) 2k (a0-a9, a11) 1k (a0?a9) table 3: speed grade compatibility marking pc3200 (3-3-3) pc2700 (2.5-3-3) pc2100 (2-2-2) pc2100 (2-3-3) pc2100 (2.5-3-3) pc1600 (2-2-2) -5b 1 yes yes yes yes yes yes -6 ? yes yes yes yes yes -6t ? yes yes yes yes yes -75e ??yesyesyesyes -75z ?? ?yesyesyes -75 ?? ??yesyes -5b -6/-6t -75e -75z -75 -75 example part number: mt46v32m16p-6t:f l special options standard low power speed grade t ck = 5ns, cl = 3 t ck = 6ns, cl = 2.5 t ck = 6ns, cl = 2.5 -5b -6 -6t it operating temp commercial industrial revision x4, x8, x16 x4, x8, x16 :f :j configuration mt46v package speed revision sp. op. temp. configuration 128 meg x 4 64 meg x 8 32 meg x 16 128m4 64m8 32m16 package 400-mil tsop 400-mil tsop (pb-free) 10mm x 12.5mm fbga 10mm x 12.5mm fbga (pb-free) 8mm x 12.5mm fbga 8mm x 12.5mm fbga (pb-free) tg p fn bn cv cy - :
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddrtoc.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 3 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram table of contents table of contents state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin and ball assignments and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 electrical specifications ? i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 electrical specifications ? dc and ac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 load mode register (lmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 active (act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 precharge (pre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 burst terminate (bst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 auto refresh (ar). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 power-down (cke not active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core1.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 4 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram state diagram state diagram figure 2: simplified state diagram note: this diagram represents operations within a single bank only and does not capture concur- rent operations in other banks. power on power applie d ref s lmr refa ref s x a c t c ke low c kel c ke hi g h c keh pre pre c har g e all b anks mr emr s elf refresh i d le all b anks pre c har g e d row a c tive burst stop rea d rea d a automati c sequen c e c omman d sequen c e write write write write a write a pre c har g e preall a c tive power- d own pre c har g e power- d own auto refresh pre write a read a read a pre pre read a read read read b s t a c t = a c tive b s t = bur s t terminate c keh = exit power- d own c kel = enter power- d own emr = exten d e d mo d e re g ister lmr = load mode re g i s ter mr = mo d e re g ister pre = pre c har g e preall = pre c har g e all b anks read a = read with auto pre c har g e refa = auto refre s h ref s = enter self refresh ref s x = exit self refresh write a = write with auto pre c har g e pre lmr
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core1.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 5 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram functional description functional description the ddr sdram uses a double data rate architec ture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture with an inter- face designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram effe ctively consists of a single 2 n -bit-wide, one-clock- cycle data transfer at the internal dram core and two corresponding n -bit-wide, one- half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmit ted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller duri ng writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte and one for the upper byte. the ddr sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are register ed at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram ar e burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which may then be followed by a read or write command. the add ress bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincide nt with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdr sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby prov iding high effective bandw idth by hiding row precharge and activation time. an auto refresh mode is prov ided, along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all full-drive option outputs are sstl_2, class ii compatible. general notes ? the functionality and the timing specifications discussed in this data sheet are for the dll-enabled mode of operation. ? throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq coll ectively, unless spec ifically stated otherwise. additionally, the x16 is divided into two bytes, the lower byte and upper byte. for the lower byte (dq[7:0]) dm refers to ldm and dqs refers to ldqs. for the upper byte (dq[15:8]) dm refers to udm and dqs refers to udqs. ? complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes prece dence over a general statement.
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 6 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram functional block diagrams functional block diagrams the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a 4-bank dram. figure 3: 128 meg x 4 functional block diagram 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 12 command decode a0?a12, ba0, ba1 cke 13 address register 15 2048 (x8) 16384 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 2,048 x 8) bank0 row- address latch & decoder 8192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 11 1 2 2 refresh counter 4 4 4 1 input registers 1 1 1 1 rcvrs 1 8 8 2 8 data dqs mask data ck ck col0 drvrs dll mux dqs generator 4 4 4 4 4 8 1 read latch write fifo & drivers col0 dq0?dq3 ck out ck in dqs dm
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 7 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram functional block diagrams figure 4: 64 meg x 8 functional block diagram figure 5: 32 meg x 16 functional block diagram 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 11 command decode a0?a12, ba0, ba1 cke 13 address register 15 1024 (x16) 16384 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 1,024 x 16) bank0 row- address latch & decoder 8192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 10 2 2 refresh counter 8 8 8 1 input registers 1 1 1 1 rcvrs 1 16 16 2 16 data dqs mask data ck ck drvrs dll mux dqs generator 8 8 8 8 8 16 1 read latch write fifo & drivers 1 col0 col0 ck out ck in dq0?dq7 dqs dm 13 ra s # c a s # row- addre ss mux c k cs # we# c k# c ontrol lo g i c c olumn- addre ss c ounter/ lat c h mode re g i s ter s 10 c ommand de c ode a0?a12, ba0, ba1 c ke 13 addre ss re g i s ter 15 512 (x32) 1 6 384 i/o g atin g dm ma s k lo g i c c olumn de c oder bank0 memory array (8,192 x 512 x 32) bank0 row- addre ss lat c h & de c oder 8192 s en s e amplifier s bank c ontrol lo g i c 15 bank1 bank2 bank3 13 9 2 2 refre s h c ounter 1 6 1 6 1 6 2 input re g i s ter s 2 2 2 2 r c vr s 2 32 32 4 32 c k out data dq s ma s k data c k c k c k in drvr s dll mux dq s g enerator 1 6 1 6 1 6 1 6 1 6 32 dq0?dq15 ldq s , udq s 2 read lat c h write fifo & driver s 1 c ol0 c ol0 ldm, udm
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 8 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram pin and ball assignments and descriptions pin and ball assignments and descriptions figure 6: 66-pin tsop pin assignment (top view) x4 x16 x4 x8 x16 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss q udqs dnu v ref v ss udm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss v ss nf v ss q nc dq3 v dd q nc nf v ss q nc dq2 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v dd q ldqs nc v dd dnu ldm we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x8 v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd v dd nf v dd q nc dq0 v ss q nc nf v dd q nc dq1 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 9 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram pin and ball assignments and descriptions figure 7: 60-ball fbga ball assignment (top view) v ss q dq14 dq12 dq10 dq8 v ref dq15 v dd q v ss q v dd q v ss q v ss ck a12 a11 a8 a6 a4 v ss dq13 dq11 dq9 udqs udm ck# cke a9 a7 a5 v ss v dd dq2 dq4 dq6 ldqs ldm we# ras# ba1 a0 a2 v dd dq0 v ss q v dd q v ss q v dd q v dd cas# cs# ba0 a10 a1 a3 v dd q dq1 dq3 dq5 dq7 x16 (top view) v ss q nc nc nc nc v ref nf v dd q v ss q v dd q v ss q v ss ck a12 a11 a8 a6 a4 v ss dq3 nf dq2 dqs dm ck# cke a9 a7 a5 v ss v dd dq0 nf dq1 nc nc we# ras# ba1 a0 a2 v dd nf v ss q v dd q v ss q v dd q v dd cas# cs# ba0 a10 a1 a3 v dd q nc nc nc nc x4 (top view) v ss q nc nc nc nc v ref dq7 v dd q v ss q v dd q v ss q v ss ck a12 a11 a8 a6 a4 v ss dq6 dq5 dq4 dqs dm ck# cke a9 a7 a5 v ss v dd dq1 dq2 dq3 nc nc we# ras# ba1 a0 a2 v dd dq0 v ss q v dd q v ss q v dd q v dd cas# cs# ba0 a10 a1 a3 v dd q nc nc nc nc x8 (top view) a 12 3456789 b c d e f g h j k l m a 12 3456789 b c d e f g h j k l m a 12 3456789 b c d e f g h j k l m dnu dnu dnu
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 10 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram pin and ball assignments and descriptions table 4: pin and ball descriptions fbga numbers tsop numbers symbol type description k7, l8, l7, m8, m2, l3, l2, k3, k2, j3, k8, j2, h2 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 28 41, 42 a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inputs also provide the op-code during a load mode register command. j8, j7 26, 27 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is bei ng applied. ba0 and ba1 also define which mode register (mode register or extended mode register) is loaded during the load mode register (lmr) command. g2, g3 45, 46 ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossi ng of the positive edge of ck and negative edge of ck#. output data (dq and dqs) is referenced to the crossings of ck and ck#. h3 44 cke input clock enable: cke high activates and cke low deactivates the internal clock, input buffers, and output drivers. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous fo r power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout re ad and write accesses. input buffers (excluding ck, ck#, and cke) are disabl ed during power-down. input buffers (excludi ng cke) are disab led during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied and until cke is first brought high, after which it becomes a sstl_2 input only. h8 24 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. f3 f7, f3 47 20,47 dm ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. for the x16, ldm is dm for dq[7:0] and udm is dm for dq[15:8]. pin 20 is a nc on x4 and x8. h7, g8, g7 23, 22, 21 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. a8, b9, b7, c9, c7, d9, d7, e9, e1, d3, d1, c3, c1, b3, b1, a2 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq[2:0] dq[5:3] dq[8:6] dq[11:9] dq[14:12] dq15 i/o data input/output: data bus for x16. a8, b7, c7, d7, d3, c3, b3, a2 2, 5, 8, 11, 56, 59, 62, 65 dq[2:0] dq[5:3] dq6, dq7 i/o data input/output: data bus for x8. b7, d7, d3, b3 5, 11, 56, 62 dq[2:0] dq3 i/o data input/output: data bus for x4.
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 11 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram pin and ball assignments and descriptions e3 e7 e3 51 16 51 dqs ldqs udqs i/o data strobe: output with read dat a, input with write data. dqs is edge- aligned with read data, centered in write data. it is used to capture data. for the x16, ldqs is dqs for dq[7:0] and udqs is dqs for dq[15:8]. pin 16 (e7) is nc on x4 and x8. f8, m7, a7 1, 18, 33 v dd supply power supply: 2.5v 0.2v. (2.6v 0.1v for ddr400). b2, d2, c8, e8, a9 3, 9, 15, 55, 61 v ddq supply dq power supply: 2.5v 0.2v (2.6v 0.1v for ddr400). isolated on the die for improved noise immunity. f1 49 v ref supply sstl_2 reference voltage. a3, f2, m3 34, 48, 66 v ss supply ground. a1, c2, e2, b8, d8 6, 12, 52, 58, 64 v ssq supply dq ground: isolated on the die for improved noise immunity. ? 14, 17, 25, 43, 53 nc ? no connect for x16: these pins should be left unconnected. b1, b9, c1, c9, d1, d9, e1, e7, e9, f7 4, 7, 10, 13, 14, 16, 17, 20, 25, 43, 53, 54, 57, 60, 63 nc ? no connect for x8: these pins should be left unconnected. b1, b9, c1, c9, d1, d9, e1, e7, e9, f7 4, 7, 10, 13, 14, 16, 17, 20, 25, 43, 53, 54, 57, 60, 63 nc ? no connect for x4: these pins should be left unconnected. a2, a8, c3, c7 2, 8, 59, 65 nf ? no function for x4: these pins should be left unconnected. f9 19, 50 dnu ? do not use: must float to minimize noise on v ref . table 5: reserved nc pin and ball descriptions nc pins not listed may also be reserved for other us es; this table defines nc pins of importance tsop numbers symbol type description 17 a13 input address input a13 for 1gb devices. table 4: pin and ball descriptions (continued) fbga numbers tsop numbers symbol type description
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 12 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram package dimensions package dimensions figure 8: 66-pin plastic tsop (400 mil) notes: 1. all dimen sions are in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. not all packages will have the half moon shaped notches as shown. see detail a 0.10 0.65 typ 0.71 10.16 0.08 0.15 0.50 0.10 pin #1 id detail a 22.22 0.08 0.32 .075 typ +0.03 ?0.02 +0.10 ?0.05 1.20 max 0.10 0.25 0.80 typ 0.10 (2x) gage plane 11.76 0.20
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 13 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram package dimensions figure 9: 60-ball fbga (10mm x 12.5mm) notes: 1. all dimen sions are in millimeters. 2. topside part marking decoder can be found on micron?s web site. ball #1 id solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder ball pad: ? .33 non solder mask defined mold compound: epoxy novolac substrate: plastic laminate 1.20 max 0 . 8 5 0 . 0 5 0.10 c c seating plane ball a1 id ball a1 c l c l .45 60x ? solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40. ball a9 11.00 5.50 0.05 6.25 0.05 12.50 0.10 1.00 typ 6.40 1.80 ctr 0.80 (typ) 3.20 0.05 5.00 0.05 10.00 0.10
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 14 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram package dimensions figure 10: 60-ball fbga (8mm x 12.5mm) notes: 1. all dimen sions are in millimeters. 2. topside part marking decoder can be found on micron?s web site. ball a1 id 1.20 max 8 0.15 ball a1 id 60x ?0.45 solder ball material: eutectic or sac305. dimensions apply to solder balls post- reflow on ?0.33 nsmd ball pads. 1 typ 11 ctr 12.5 0.15 0.8 0.1 0.12 a a seating plane 6.4 ctr 0.8 typ 0.25 min 9 8 7 3 2 1 a b c d e f g h j k l m
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 15 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? i dd electrical specifications ? i dd ta bl e 6 : i dd specifications and conditions (x4, x8) die revision f only v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v (-5b); v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v (-6, -6t, -75e, -75z, -75); 0c t a 70c; notes: 1?5, 11, 13, 15, 47; notes appear on pages 37?42; see also table 10 on page 20 parameter/condition symbol -5b -6/6t -75e -75z/-75 units notes operating one-bank active -precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 155 130 130 115 ma 23, 48 operating one-bank active-re ad-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 185 160 160 145 ma 23, 48 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p 55 5 5 ma 24, 33 idle standby current: cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd2f 55 45 45 40 ma 51 active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low i dd3p 45 35 35 30 ma 24, 33 active standby current: cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 60 50 50 45 ma 23 operating burst read current : burst = 2; continuous burst reads; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 190 165 165 145 ma 23, 48 operating burst write current: burst = 2; continuous burst writes; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 195 175 155 135 ma 23 auto refresh burst current: t rfc = t rfc (min) i dd5 345 290 290 280 ma 50 t rfc = 7.8s i dd5a 11 10 10 10 ma 28, 50 t rfc = 1.95s i dd5a 16 15 15 15 ma 28, 50 self refresh current: cke 0.2v standard i dd6 55 5 5 ma 12 low power (l) i dd6a 33 3 3 ma 12 operating bank interlea ve read current: four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 450 405 400 350 ma 23, 49
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 16 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? i dd ta bl e 7 : i dd specifications and conditions (x16) die revision f only v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v (-5b); v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v (-6, -6t, -75e, -75z, -75); 0c t a 70c; notes: 1?5, 11, 13, 15, 47; notes appear on pages 37?42; see also table 10 on page 20 parameter/condition symbol -5b -6/6t -75e -75z/-75 units notes operating one-bank active -precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 155 130 130 115 ma 23, 48 operating one-bank active-re ad-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 195 160 160 145 ma 23, 48 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p 5 5 5 5 ma 24, 33 idle standby current: cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd2f 55 45 45 40 ma 51 active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low i dd3p 45 35 35 30 ma 24, 33 active standby current: cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 60 50 50 45 ma 23 operating burst read current : burst = 2; continuous burst reads; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 210 165 165 145 ma 23, 48 operating burst write current: burst = 2; continuous burst writes; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 215 195 160 135 ma 23 auto refresh burst current: t rfc = t rfc (min) i dd5 345 290 290 280 ma 50 t rfc = 7.8s i dd5a 11 10 10 10 ma 28, 50 t rfc = 1.95s i dd5a 16 15 15 15 ma 28, 50 self refresh current: cke 0.2v standard i dd6 65 5 5 ma 12 low power (l) i dd6a 43 3 3 ma 12 operating bank interlea ve read current: four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 480 405 400 350 ma 23, 49
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 17 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? i dd ta bl e 8 : i dd specifications and conditions (x4, x8) die revision j only v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v (-5b); v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v (-6, -6t,); 0c t a 70c; notes: 1?5, 11, 13, 15, 47; notes appear on pages 37?42; see also table 10 on page 20 parameter/condition symbol -5b -6/6t units notes operating one-bank active -precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 75 65 ma 23, 48 operating one-bank active-re ad-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 85 75 ma 23, 48 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p 5 5 ma 24, 33 idle standby current: cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd2f 23 23 ma 51 active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low i dd3p 18 14 ma 24, 33 active standby current: cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 40 38 ma 23 operating burst read current : burst = 2; continuous burst reads; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 120 85 ma 23, 48 operating burst write current: burst = 2; continuous burst writes; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 120 95 ma 23 auto refresh burst current: t rfc = t rfc (min) i dd5 120 105 ma 50 t rfc = 7.8s i dd5a 8 8 ma 28, 50 self refresh current: cke 0.2v standard i dd6 55ma12 low power (l) i dd6a 33ma12 operating bank interlea ve read current: four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 230 210 ma 23, 49
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 18 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? i dd ta bl e 9 : i dd specifications and conditions (x16) die revision j only v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v (-5b); v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v (-6, -6t); 0c t a 70c; notes: 1?5, 11, 13, 15, 47; notes appear on pages 37?42; see also table 10 on page 20 parameter/condition symbol -5b -6/6t units notes operating one-bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 75 65 ma 23, 48 operating one-bank active-r ead-precharge current: burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 85 75 ma 23, 48 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p 5 5 ma 24, 33 idle standby current: cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd2f 23 23 ma 51 active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low i dd3p 18 14 ma 24, 33 active standby current: cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 40 38 ma 23 operating burst read current : burst = 2; continuous burst reads; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 125 95 ma 23, 48 operating burst write current: burst = 2; continuous burst writes; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 120 95 ma 23 auto refresh burst current: t rfc = t rfc (min) i dd5 125 110 ma 50 t rfc = 7.8s i dd5a 8 8 ma 28, 50 self refresh current: cke 0.2v standard i dd6 55 ma 12 low power (l) i dd6a 33 ma 12 operating bank interleave read current: four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 230 210 ma 23, 49
pdf: 09005aef80a1d9d4/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. 512mb_ddr_x4x8x16_d2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 19 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? i dd table 10: i dd test cycle times values reflect number of clock cycles for each test i dd te s t speed grade clock cycle time t rrd t rcd t ras t rp t rc t rfc t refi cl i dd 0 -75/75z 7.5ns n/a n/a 6 3 9 n/a n/a n/a -75e 7.5ns n/a n/a 6 2 8 n/a n/a n/a -6/-6t 6ns n/a n/a 7 3 10 n/a n/a n/a -5b 5ns n/a n/a 8 3 11 n/a n/a n/a i dd 1 -75 7.5ns n/a n/a 6 3 9 n/a n/a 2.5 -75z 7.5ns n/a n/a 6 3 9 n/a n/a 2 -75e 7.5ns n/a n/a 6 2 8 n/a n/a 2 -6/-6t 6ns n/a n/a 7 3 10 n/a n/a 2.5 -5b 5ns n/a n/a n/a n/a n/a n/a n/a 3 i dd 4r -75 7.5ns n/a n/a n/a n/a n/a n/a n/a 2.5 -75z 7.5ns n/a n/a n/a n/a n/a n/a n/a 2 -75e 7.5ns n/a n/a n/a n/a n/a n/a n/a 2 -6/-6t 6ns n/a n/a n/a n/a n/a n/a n/a 2.5 -5b 5ns n/a n/a n/a n/a n/a n/a n/a 3 i dd 4w -75 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a -75z 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a -75e 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a -6/-6t 6ns n/a n/a n/a n/a n/a n/a n/a n/a -5b 5ns n/a n/a n/a n/a n/a n/a n/a n/a i dd 5 -75/75z 7.5ns n/a n/a n/a n/a n/a 10 10 n/a -75e 7.5ns n/a n/a n/a n/a n/a 9 9 n/a -6/-6t 6ns n/a n/a n/a n/a n/a 12 12 n/a -5b 5ns n/a n/a n/a n/a n/a 14 14 n/a i dd 5a -75/75z 7.5ns n/a n/a n/a n/a n/a 10 1,029 n/a -75e 7.5ns n/a n/a n/a n/a n/a 10 1,029 n/a -6/-6t 6ns n/a n/a n/a n/a n/a 12 1,288 n/a -5b 5ns n/a n/a n/a n/a n/a 14 1,546 n/a i dd 7 -75 7.5ns 2 3 n/a 3 10 n/a n/a 2.5 -75z 7.5ns 2 3 n/a 3 10 n/a n/a 2 -75e 7.5ns 2 3 n/a 2 8 n/a n/a 2 -6/-6t 6ns 2 3 n/a 3 10 n/a n/a 2.5 -5b 5ns 2 3 n/a 3 11 n/a n/a 3
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 20 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac electrical specifications ? dc and ac stresses greater than those listed in table 11 may cause permanent damage to the device. this is a stress rating onl y, and functional operation of the device at these or any other conditions above those indi cated in the operational section s of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 11: absolute maximum ratings parameter min max units v dd supply voltage relative to v ss ?1v 3.6v v v ddq supply voltage relative to v ss ?1v 3.6v v v ref and inputs voltage relative to v ss ?1v 3.6v v i/o pins voltage relative to v ss ?0.5v v ddq + 0.5v v storage temperature (plastic) ?55 150 c short circuit output current ?50ma table 12: dc electrical characteristics and operating conditions (-5b) notes: 1?5 and 17 apply to the entire table; notes appear on page 37; v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v parameter/condition symbol min max units notes supply voltage v dd 2.5 2.7 v 37, 42 i/o supply voltage v ddq 2.5 2.7 v 37, 42, 45 i/o reference voltage v ref 0.49 v ddq 0.51 v ddq v7, 45 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 8, 45 input high (logic 1) voltage v ih(dc) v ref + 0.15 v dd + 0.3 v 29 input low (logic 0) voltage v il(dc) ?0.3 v ref - 0.15 v 29 input leakage current: any input 0v v in v dd , v ref pin 0v v in 1.35v (all other pins not under test = 0v) i i ?2 2 a output leakage current: (dq are disabled; 0v v out v dd q ) i oz ?5 5 a full-drive option output levels (x4, x8, x16): high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) i oh ?16.8 ? ma 38, 40 low current (v out = 0.373v, maximum v ref , maximum v tt ) i ol 16.8 ? ma reduced-drive option output levels: high current (v out = v ddq - 0.373v, minimum v ref , minimum v tt ) i ohr ?9 ? ma 39, 40 low current (v out = 0.373v, maximum v ref , maximum v tt ) i olr 9?ma ambient operating temperatures commercial t a 070c industrial t a ?40 85 c
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 21 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 13: dc electrical characteristics and operating conditions (-6, -6t, -75e, -75z, -75) notes: 1?5 and 17 apply to the entire table; notes appear on page 37; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 37, 42 i/o supply voltage v ddq 2.3 2.7 v 37, 42, 45 i/o reference voltage v ref 0.49 v ddq 0.51 v ddq v7, 45 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 8, 45 input high (logic 1) voltage v ih(dc) v ref + 0.15 v dd + 0.3 v 29 input low (logic 0) voltage v il(dc) ?0.3 v ref - 0.15 v 29 input leakage current: any input 0v v in v dd , v ref pin 0v v in 1.35v (all other pins not under test = 0v) i i ?2 2 a output leakage current: (dq are disabled; 0v v out v ddq ) i oz ?5 5 a full-drive option output levels (x4, x8, x16): high current (v out = v ddq - 0.373v, minimum v ref , minimum v tt ) i oh ?16.8 ? ma 38, 40 low current (v out = 0.373v, maximum v ref , maximum v tt ) i ol 16.8 ? ma reduced-drive option output levels: high current (v out = v ddq - 0.373v, minimum v ref , minimum v tt ) i ohr ?9 ? ma 39, 40 low current (v out = 0.373v, maximum v ref , maximum v tt ) i olr 9?ma ambient operating temperatures commercial t a 070c industrial t a ?40 85 c table 14: ac input operating conditions notes: 1?5 and 17 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v (v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v for -5b) parameter/condition symbol min max units notes input high (logic 1) voltage v ih(ac) v ref + 0.310 ? v 15, 29, 41 input low (logic 0) voltage v il(ac) ?v ref - 0.310 v 15, 29, 41 i/o reference voltage v ref(ac) 0.49 v ddq 0.51 v ddq v7
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 22 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac figure 11: input voltage waveform notes: 1. v oh,min with test load is 1.927v. 2. v ol,max with test load is 0.373v. 3. numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5b. 0.940v 1.100v 1.200v 1.225v 1.250v 1.275v 1.300v 1.400v 1.5 6 0v v il ( ac ) v il ( dc ) v ref - a c noise v ref - d c error v ref + d c error v ref + a c noise re c eiver transmitter v ih ( dc ) v ih ( ac ) v oh (min) (1.670v 1 for sstl_2 termination) v in ( ac ) - provides margin between v ol (max) and v il ( ac ) vssq v dd q (2.3v min) v ol (max) (0.83v 2 for sstl_2 termination) s ystem noise mar g in (power/ g roun d , c rosstalk, si g nal inte g rity attenuation) referen c e point 25 25 v tt
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 23 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac figure 12: sstl_2 clock input notes: 1. ck or ck# may not be more positive than v ddq + 0.3v or more negative than v ss - 0.3v. 2. this provides a minimum of 1.15v to a maximum of 1.35v and is always half of v ddq . 3. ck and ck# must cross in this region. 4. ck and ck# must meet at least v id(dc) ,min when static and is centered around v mp(dc) . 5. ck and ck# must have a minimum 700mv peak-to-peak swing. 6. for ac operation, all dc clock re q uirements must also be satisfied. 7. numbers in diagram reflect nominal values for all devices other than -5b. table 15: clock input operating conditions notes: 1?5, 16, 17, and 31 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v (v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v for -5b) parameter/condition symbol min max units notes clock input mid-point voltage: ck and ck# v mp(dc) 1.15 1.35 v 7, 10 clock input voltage level: ck and ck# v in(dc) ?0.3 v ddq + 0.3 v 7 clock input differential voltage: ck and ck# v id(dc) 0.36 v ddq + 0.6 v 7, 9 clock input differential voltage: ck and ck# v id(ac) 0.7 v ddq + 0.6 v 9 clock input crossing point voltage: ck and ck# v ix(ac) 0.5 v ddq - 0.2 0.5 v ddq + 0.2 v 10 c k c k# 2.80v maximum c lo c k level 1 minimum c lo c k level 1 ?0.30v 1.25v 1.45v 1.05v v id ( a c ) 5 v id ( d c ) 4 x v mp ( d c ) 2 v ix ( a c ) 3 x
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 24 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 16: capacitance (x4, x8 tsop) note: 14 applies to the en tire table; notes appear on page 37 parameter symbol min max units notes delta input/ou tput capacitance: dq[3:0] (x4), dq[7:0] (x8) dc io ?0.50pf 25 delta input capacitance: command and address dc i1 ?0.50pf 30 delta input capacitance: ck, ck# dc i2 ?0.25pf 30 input/output capacitance: dq, dqs, dm c io 4.0 5.0 pf input capacitance: command and address c i1 2.0 3.0 pf input capacitance: ck, ck# c i2 2.0 3.0 pf input capacitance: cke c i3 2.0 3.0 pf table 17: capacitance (x4, x8 fbga) note: 14 applies to the en tire table; notes appear on page 37 parameter symbol min max units notes delta inpu t/output capacitance: dq, dqs, dm dc io ?0.50pf 25 delta input capacitance: command and address dc i1 ?0.50pf 30 delta input capacitance: ck, ck# dc i2 ?0.25pf 30 input/output capacitance: dq, dqs, dm c io 3.5 4.5 pf input capacitance: command and address c i1 1.5 2.5 pf input capacitance: ck, ck# c i2 1.5 2.5 pf input capacitance: cke c i3 1.5 2.5 pf table 18: capacitance (x16 tsop) note: 14 applies to the en tire table; notes appear on page 37 parameter symbol min max units notes delta input/output capacitance: dq[7:0], ldqs, ldm dc iol ?0.50pf 25 delta input/output capacitance: dq[15:8], udqs, udm dc iou ?0.50pf 25 delta input capacitance: command and address dc i1 ?0.50pf 30 delta input capacitance: ck, ck# dc i2 ?0.25pf 30 input/output capacitance: dq, ldqs, udqs, ldm, udm c io 4.0 5.0 pf input capacitance: command and address c i1 2.0 3.0 pf input capacitance: ck, ck# c i2 2.0 3.0 pf input capacitance: cke c i3 2.0 3.0 pf table 19: capacitance (x16 fbga) note: 14 applies to the en tire table; notes appear on page 37 parameter symbol min max units notes delta input/output capacitance: dq[7:0], ldqs, ldm dc iol ?0.50pf 25 delta input/output capacitance: dq[15:8], udqs, udm dc iou ?0.50pf 25 delta input capacitance: command and address dc i1 ?0.50pf 30 delta input capacitance: ck, ck# dc i2 ?0.25pf 30 input/output capacitance: dq, ldqs, udqs, ldm, udm c io 3.5 4.5 pf input capacitance: command and address c i1 1.5 2.5 pf input capacitance: ck, ck# c i2 1.5 2.5 pf input capacitance: cke c i3 1.5 2.5 pf
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 25 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 20: electrical characteristics and recommended ac operating conditions (-5b) notes 1?6, 16?18, and 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v ac characteristics -5b units notes parameter symbol min max access window of dq from ck/ck# t ac ?0.70 0.70 ns ck high-level width t ch 0.45 0.55 t ck 31 clock cycle time cl = 3 t ck (3) 5 7.5 ns 52 cl = 2.5 t ck (2.5) 6 13 ns 46, 52 cl = 2 t ck (2) 7.5 13 ns 46, 52 ck low-level width t cl 0.45 0.55 t ck 31 dq and dm input hold time relative to dqs t dh 0.40 ? ns 27, 32 dq and dm input pulse width (for each input) t dipw 1.75 ? ns 32 access window of dqs from ck/ck# t dqsck ?0.60 0.60 ns dqs input high pulse width t dqsh 0.35 ? t ck dqs input low pulse width t dqsl 0.35 ? t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.40 ns 26, 27 write command to first dqs latching transition t dqss 0.72 1.28 t ck dq and dm input setup time relative to dqs t ds 0.40 ? ns 27, 32 dqs falling edge from ck rising ? hold time t dsh 0.2 ? t ck dqs falling edge to ck rising ? setup time t dss 0.2 ? t ck half-clock period t hp t ch, t cl ? ns 35 data-out high-z window from ck/ck# t hz ? 0.70 ns 19, 43 address and control input hold time (slew rate 0.5 v/ns) t ih f 0.60 ? ns 15 address and control input pulse width (for each input) t ipw 2.2 ? ns address and control input setup time (slew rate 0.5 v/ns) t is f 0.60 ? ns 15 data-out low-z window from ck/ck# t lz ?0.70 ? ns 19, 43 load mode register command cycle time t mrd 10 ? ns dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? ns 26, 27 data hold skew factor t qhs ? 0.50 ns active-to-read with auto precharge command t rap 15 ? ns active-to-precharge command t ras 40 70,000 ns 36 active-to-active/auto refresh command period t rc 55 ? ns 55 active-to-read or write delay t rcd 15 ? ns refresh-to-refresh command interval t refc ? 70.3 s 24 average periodic refresh interval t refi ? 7.8 s 24 auto refresh command period t rfc 70 ? ns 50 precharge command period t rp 15 ? ns dqs read preamble t rpre 0.9 1.1 t ck 44 dqs read postamble t rpst 0.4 0.6 t ck 44 active bank a to active bank b command t rrd 10 ? ns terminating voltage delay to v dd t vtd 0 ? ns dqs write preamble t wpre 0.25 ? t ck dqs write preamble setup time t wpres 0 ? ns 21, 22 dqs write postamble t wpst 0.4 0.6 t ck 20 write recovery time t wr 15 ? ns internal write-to-read command delay t wtr 2 ? t ck
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 26 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac exit self refresh-to-non-read command t xsnr 70 ? ns exit self refresh-to-read command t xsrd 200 ? t ck data valid output window n/a t qh - t dqsq ns 26 table 20: electrical characteristics and recommended ac operating conditions (-5b) (continued) notes 1?6, 16?18, and 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.6v 0.1v, v dd = 2.6v 0.1v ac characteristics -5b units notes parameter symbol min max
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 27 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 21: electrical characteristics and recommended ac operating conditions (-6) notes: 1?6, 16?18, 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -6 (fbga) units notes parameter symbol min max access window of dq from ck/ck# t ac ?0.70 0.70 ns ck high-level width t ch 0.45 0.55 t ck 31 clock cycle time cl = 2.5 t ck (2.5) 6 13 ns 46, 52 cl = 2 t ck (2) 7.5 13 ns 46, 52 ck low-level width t cl 0.45 0.55 t ck 31 dq and dm input hold time relative to dqs t dh 0.45 ? ns 27, 32 dq and dm input pulse width (for each input) t dipw 1.75 ? ns 32 access window of dqs from ck/ck# t dqsck ?0.6 0.6 ns dqs input high pulse width t dqsh 0.35 ? t ck dqs input low pulse width t dqsl 0.35 ? t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.4 ns 26, 27 write command to first dqs latching transition t dqss 0.75 1.25 t ck dq and dm input setup time relative to dqs t ds 0.45 ? ns 27, 32 dqs falling edge from ck rising - hold time t dsh 0.2 ? t ck dqs falling edge to ck rising - setup time t dss 0.2 ? t ck half-clock period t hp t ch, t cl ? ns 35 data-out high-z window from ck/ck# t hz ? 0.7 ns 19, 43 address and control input hold time (fast slew rate) t ih f 0.75 ? ns address and control input hold time (slow slew rate) t ih s 0.8 ? ns 15 address and control input pulse width (for each input) t ipw 2.2 ? ns address and control input setup time (fast slew rate) t is f 0.75 ? ns address and control input setup time (slow slew rate) t is s 0.8 ? ns 15 data-out low-z window from ck/ck# t lz ?0.7 ? ns 19, 43 load mode register command cycle time t mrd 12 ? ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? ns 26, 27 data hold skew factor t qhs ? 0.50 ns active-to-read with auto precharge command t rap 15 ? ns active-to-precharge command t ras 42 70,000 ns 36, 54 active-to-active/auto refresh command period t rc 60 ? ns 55 active-to-read or write delay t rcd 15 ? ns refresh-to-refresh command interval t refc ? 70.3 s 24 average periodic refresh interval t refi ? 7.8 s 24 auto refresh command period t rfc 72 ? ns 50 precharge command period t rp 15 ? ns dqs read preamble t rpre 0.9 1.1 t ck 44 dqs read postamble t rpst 0.4 0.6 t ck 44 active bank a to active bank b command t rrd 12 ? ns terminating voltage delay to v ss t vtd 0 ? ns dqs write preamble t wpre 0.25 ? t ck dqs write preamble setup time t wpres 0 ? ns 21, 22 dqs write postamble t wpst 0.4 0.6 t ck 20 write recovery time t wr 15 ? ns
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 28 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac internal write-to-read command delay t wtr 1 ? t ck exit self refresh-to-non-read command t xsnr 75 ? ns exit self refresh-to-read command t xsrd 200 ? t ck data valid output window n/a t qh - t dqsq ns 26 table 21: electrical characteristics and recommended ac operating conditions (-6) (continued) notes: 1?6, 16?18, 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -6 (fbga) units notes parameter symbol min max
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 29 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 22: electrical characteristics and recommended ac operating conditions (-6t) notes: 1?6, 16?18, and 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -6t (tsop) units notes parameter symbol min max access window of dq from ck/ck# t ac ?0.70 0.70 ns ck high-level width t ch 0.45 0.55 t ck 31 clock cycle time cl = 2.5 t ck (2.5) 6 13 ns 46, 52 cl = 2 t ck (2) 7.5 13 ns 46, 52 ck low-level width t cl 0.45 0.55 t ck 31 dq and dm input hold time relative to dqs t dh 0.45 ? ns 27, 32 dq and dm input pulse width (for each input) t dipw 1.75 ? ns 32 access window of dqs from ck/ck# t dqsck ?0.6 0.6 ns dqs input high pulse width t dqsh 0.35 ? t ck dqs input low pulse width t dqsl 0.35 ? t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.45 ns 26, 27 write command to first dqs latching transition t dqss 0.75 1.25 t ck dq and dm input setup time relative to dqs t ds 0.45 ? ns 27, 32 dqs falling edge from ck rising - hold time t dsh 0.2 ? t ck dqs falling edge to ck rising - setup time t dss 0.2 ? t ck half-clock period t hp t ch, t cl ?ns35 data-out high-z window from ck/ck# t hz ? 0.7 ns 19, 43 address and control input hold time (fast slew rate) t ih f 0.75 ? ns address and control input hold time (slow slew rate) t ih s 0.8 ? ns 15 address and control input pulse width (for each input) t ipw 2.2 ? ns address and control input setup time (fast slew rate) t is f 0.75 ? ns address and control input setup time (slow slew rate) t is s 0.8 ? ns 15 data-out low-z window from ck/ck# t lz ?0.7 ? ns 19, 43 load mode register command cycle time t mrd 12 ? ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? ns 26, 27 data hold skew factor t qhs ? 0.55 ns active-to-read with auto precharge command t rap 15 ? ns active-to-precharge command t ras 42 70,000 ns 36, 54 active-to-active/auto refresh command period t rc 60 ? ns 55 active-to-read or write delay t rcd 15 ? ns refresh-to-refresh command interval t refc ? 70.3 s 24 average periodic refresh interval t refi ? 7.8 s 24 auto refresh command period t rfc 72 ? ns 50 precharge command period t rp 15 ? ns dqs read preamble t rpre 0.9 1.1 t ck 44 dqs read postamble t rpst 0.4 0.6 t ck 44 active bank a to active bank b command t rrd 12 ? ns terminating voltage delay to v ss t vtd 0 ? ns dqs write preamble t wpre 0.25 ? t ck dqs write preamble setup time t wpres 0 ? ns 21, 22 dqs write postamble t wpst 0.4 0.6 t ck 20
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 30 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac write recovery time t wr 15 ? ns internal write-to-read command delay t wtr 1 ? t ck exit self refresh-to-non-read command t xsnr 75 ? ns exit self refresh-to-read command t xsrd 200 ? t ck data valid output window n/a t qh - t dqsq ns 26 table 22: electrical characteristics and recommended ac operating conditions (-6t) (continued) notes: 1?6, 16?18, and 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -6t (tsop) units notes parameter symbol min max
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 31 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 23: electrical characteristics and recommended ac operating conditions (-75e) notes: 1?6, 16?18, 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -75e units notes parameter symbol min max access window of dq from ck/ck# t ac ?0.75 0.75 ns ck high-level width t ch 0.45 0.55 t ck 31 clock cycle time cl = 2.5 t ck (2.5) 7.5 13 ns 46, 52 cl = 2 t ck (2) 7.5 13 ns 46, 52 ck low-level width t cl 0.45 0.55 t ck 31 dq and dm input hold time relative to dqs t dh 0.5 ? ns 27, 32 dq and dm input pulse width (for each input) t dipw 1.75 ? ns 32 access window of dqs from ck/ck# t dqsck ?0.75 0.75 ns dqs input high pulse width t dqsh 0.35 ? t ck dqs input low pulse width t dqsl 0.35 ? t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.5 ns 26, 27 write command to first dqs latching transition t dqss 0.75 1.25 t ck dq and dm input setup time relative to dqs t ds 0.5 ? ns 27, 32 dqs falling edge from ck rising - hold time t dsh 0.2 ? t ck dqs falling edge to ck rising - setup time t dss 0.2 ? t ck half-clock period t hp t ch, t cl ?ns35 data-out high-z window from ck/ck# t hz ? 0.75 ns 19, 43 address and control input hold time (fast slew rate) t ih f 0.90 ? ns address and control input hold time (slow slew rate) t ih s 1?ns15 address and control input pulse width (for each input) t ipw 2.2 ? ns address and control input setup time (fast slew rate) t is f 0.90 ? ns address and control input setup time (slow slew rate) t is s 1?ns15 data-out low-z window from ck/ck# t lz ?0.75 ? ns 19, 43 load mode register command cycle time t mrd 15 ? ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? ns 26, 27 data hold skew factor t qhs ? 0.75 ns active-to-read with auto precharge command t rap 15 ? ns active-to-precharge command t ras 40 120,000 ns 36, 54 active-to-active/auto refresh command period t rc 60 ? ns 55 active-to-read or write delay t rcd 15 ? ns refresh-to-refresh command interval t refc ? 70.3 s 24 average periodic refresh interval t refi ? 7.8 s 24 auto refresh command period t rfc 75 ? ns 50 precharge command period t rp 15 ? ns dqs read preamble t rpre 0.9 1.1 t ck 44 dqs read postamble t rpst 0.4 0.6 t ck 44 active bank a to active bank b command t rrd 15 ? ns terminating voltage delay to v ss t vtd 0 ? ns dqs write preamble t wpre 0.25 ? t ck dqs write preamble setup time t wpres 0 ? ns 21, 22 dqs write postamble t wpst 0.4 0.6 t ck 20
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 32 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac write recovery time t wr 15 ? ns internal write-to-read command delay t wtr 1 ? t ck exit self refresh-to-non-read command t xsnr 75 ? ns exit self refresh-to-read command t xsrd 200 ? t ck data valid output window n/a t qh - t dqsq ns 26 table 23: electrical characteristics and recommended ac operating conditions (-75e) (continued) notes: 1?6, 16?18, 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -75e units notes parameter symbol min max
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 33 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 24: electrical characteristics and recommended ac operating conditions (-75z) notes: 1?6, 16?18, 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -75z units notes parameter symbol min max access window of dq from ck/ck# t ac ?0.75 0.75 ns ck high-level width t ch 0.45 0.55 t ck 31 clock cycle time cl = 2.5 t ck (2.5) 7.5 13 ns 46 cl = 2 t ck (2) 7.5 13 ns 46 ck low-level width t cl 0.45 0.55 t ck 31 dq and dm input hold time relative to dqs t dh 0.5 ? ns 27, 32 dq and dm input pulse width (for each input) t dipw 1.75 ? ns 32 access window of dqs from ck/ck# t dqsck ?0.75 0.75 ns dqs input high pulse width t dqsh 0.35 ? t ck dqs input low pulse width t dqsl 0.35 ? t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.5 ns 26, 27 write command-to-first dqs latching transition t dqss 0.75 1.25 t ck dq and dm input setup time relative to dqs t ds 0.5 ? ns 27, 32 dqs falling edge from ck rising ? hold time t dsh 0.2 ? t ck dqs falling edge to ck rising ? setup time t dss 0.2 ? t ck half-clock period t hp t ch, t cl ? ns 35 data-out high-z window from ck/ck# t hz ? 0.75 ns 19, 43 address and control input hold time (fast slew rate) t ih f 0.90 ? ns address and control input hold time (slow slew rate) t ih s 1?ns15 address and control input pulse width (for each input) t ipw 2.2 ? ns address and control input setup time (fast slew rate) t is f 0.90 ? ns address and control input setup time (slow slew rate) t is s 1?ns15 data-out low-z window from ck/ck# t lz ?0.75 ? ns 19, 43 load mode register command cycle time t mrd 15 ? ns dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? ns 26, 27 data hold skew factor t qhs ? 0.75 ns active-to-read with auto precharge command t rap 20 ? ns active-to-precharge command t ras 40 120,000 ns 36 active-to-active/auto refresh command period t rc 65 ? ns 55 active-to-read or write delay t rcd 20 ? ns refresh-to-refresh command interval t refc ? 70.3 s 24 average periodic refresh interval t refi ? 7.8 s 24 auto refresh command period t rfc 75 ? ns 50 precharge command period t rp 20 ? ns dqs read preamble t rpre 0.9 1.1 t ck 44 dqs read postamble t rpst 0.4 0.6 t ck 44 active bank a to active bank b command t rrd 15 ? ns terminating voltage delay to v dd t vtd 0 ? ns dqs write preamble t wpre 0.25 ? t ck dqs write preamble setup time t wpres 0 ? ns 21, 22 dqs write postamble t wpst 0.4 0.6 t ck 20 write recovery time t wr 15 ? ns
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 34 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac internal write-to-read command delay t wtr 1 ? t ck exit self refresh-to-non-read command t xsnr 75 ? ns exit self refresh-to-read command t xsrd 200 ? t ck data valid output window n/a t qh - t dqsq ns 26 table 24: electrical characteristics and recommended ac operating conditions (-75z) (continued) notes: 1?6, 16?18, 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -75z units notes parameter symbol min max
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 35 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 25: electrical characteristics and recommended ac operating conditions (-75) notes: 1?6, 16?18, and 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -75 units notes parameter symbol min max access window of dq from ck/ck# t ac ?0.75 0.75 ns ck high-level width t ch 0.45 0.55 t ck 31 clock cycle time cl = 2.5 t ck (2.5) 7.5 13 ns 46 cl = 2 t ck (2) 10 13 ns 46 ck low-level width t cl 0.45 0.55 t ck 31 dq and dm input hold time relative to dqs t dh 0.5 ? ns 27, 32 dq and dm input pulse width (for each input) t dipw 1.75 ? ns 32 access window of dqs from ck/ck# t dqsck ?0.75 0.75 ns dqs input high pulse width t dqsh 0.35 ? t ck dqs input low pulse width t dqsl 0.35 ? t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.5 ns 26, 27 write command-to-first dqs latching transition t dqss 0.75 1.25 t ck dq and dm input setup time relative to dqs t ds 0.5 ? ns 27, 32 dqs falling edge from ck rising ? hold time t dsh 0.2 ? t ck dqs falling edge to ck rising ? setup time t dss 0.2 ? t ck half-clock period t hp t ch, t cl ? ns 35 data-out high-z window from ck/ck# t hz ? 0.75 ns 19, 43 address and control input hold time (fast slew rate) t ih f 0.90 ? ns address and control input hold time (slow slew rate) t ih s 1?ns15 address and control input pulse width (for each input) t ipw 2.2 ? ns address and control input setup time (fast slew rate) t is f 0.90 ? ns address and control input setup time (slow slew rate) t is s 1?ns15 data-out low-z window from ck/ck# t lz ?0.75 ? ns 19, 43 load mode register command cycle time t mrd 15 ? ns dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? ns 26, 27 data hold skew factor t qhs ? 0.75 ns active-to-read with auto precharge command t rap 20 ? ns active-to-precharge command t ras 40 120,000 ns 36 active-to-active/auto refresh command period t rc 65 ? ns 55 active-to-read or write delay t rcd 20 ? ns refresh-to-refresh command interval t refc ? 70.3 s 24 average periodic refresh interval t refi ? 7.8 s 24 auto refresh command period tr fc 75 ? ns 50 precharge command period t rp 20 ? ns dqs read preamble t rpre 0.9 1.1 tck 44 dqs read postamble t rpst 0.4 0.6 tck 44 active bank a to active bank b command t rrd 15 ? ns terminating voltage delay to v dd t vtd 0 ? ns dqs write preamble t wpre 0.25 ? tck dqs write preamble setup time t wpres 0 ? ns 21, 22 dqs write postamble twpst 0.4 0.6 tck 20 write recovery time twr 15 ? ns
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 36 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac internal write-to-read command delay t wtr 1 ? t ck exit self refresh-to-non-read command t xsnr 75 ? ns exit self refresh-to-read command t xsrd 200 ? t ck data valid output window n/a t qh - t dqsq ns 26 table 26: input slew rate derating values for addresses and commands note: 15 applies to the en tire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v speed slew rate t is t ih units -75z/-75e 0.500 v/ns 1.00 1 ns -75z/-75e 0.400 v/ns 1.05 1 ns -75z/-75e 0.300 v/ns 1.10 1 ns table 27: input slew rate derating values for dq, dqs, and dm note: 32 applies to the en tire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v speed slew rate t ds t dh units -75z/-75e 0.500 v/ns 0.50 0.50 ns -75z/-75e 0.400 v/ns 0.55 0.55 ns -75z/-75e 0.300 v/ns 0.60 0.60 ns table 25: electrical characteristics and recommended ac operating conditions (-75) (continued) notes: 1?6, 16?18, and 34 apply to the entire table; notes appear on page 37; 0c t a 70c; v ddq = 2.5v 0.2v, v dd = 2.5v 0.2v ac characteristics -75 units notes parameter symbol min max
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 37 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage leve ls, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. outputs (except for i dd measurements) measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environ- ment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew ra te for the input signals used to test the device is 1 v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (that is, the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. all speed grades are not offe red on all densities. re fer to page 1 for availability. 7. v ref is expected to equal v ddq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (noncommon mode) on v ref may not exceed 2% of the dc value. thus, from v ddq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 8. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, it is expected to be set equal to v ref , and it must track variations in the dc level of v ref . 9. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 10. the value of v ix and v mp is expected to equal v ddq /2 of the transmitting device and must track variations in the dc level of the same. 11. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle times at cl = 3 fo r -5b; cl = 2.5, -6/-6t/-75; and cl = 2, -75e/-75z speeds with the outputs open. 12. enables on-chip refresh and address counters. 13. i dd specifications are tested after the device is properly initialized and is averaged at the defined cycle rate. 14. this parameter is sampled. v dd = 2.5v 0.2v, v ddq = 2.5v 0.2v, v ref =v ss , f = 100 mhz, t a = 25c, v out(dc) =v ddq /2, v out (peak-to-peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 15. for slew rates less than 1 v/ns and greater than or equal to 0.5 v/ns. if the slew rate is less than 0.5 v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduction in slew rate from the 500 mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5 v/ns, functionality is uncertain. for -5b, -6, and -6t, slew rates must be greater than or equal to 0.5 v/ns. output (v out ) reference point 50 v tt 30pf
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 38 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac 16. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the in put reference level for si gnals other than ck/ck# is v ref . 17. inputs are not recognized as valid until v ref stabilizes. once initialized, including self refresh mode, v ref must be powered within specified range. exception: during the period before v ref stabilizes, cke < 0.3 v dd is recognized as low. 18. the output timing reference level, as measured at the timing refe rence point (indi- cated in note 3), is v tt . 19. t hz and t lz transitions occur in the same access time windows as data valid transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (high-z) or begins driving (low-z). 20. the intent of the ?don?t care? state after completion of the postamble is the dqs- driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ih(dc)min ) then it must not transition low (below v ih(dc) prior to t dqsh [min]). 21. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 22. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going fr om high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 23. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd mea- surements is the largest multiple of t ck that meets the maximum absolute value for t ras. 24. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. how- ever, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than 8 refresh cycles is not allowed. 25. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 26. the data valid wi ndow is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided in figure 13 on page 39 for duty cycles ranging between 50/50 and 45/55. 27. referenced to each output group: x4 = dqs with dq[3:0]; x8 = dqs with dq[7:0]; x16 = ldqs with dq[7:0] and udqs with dq[15:8]. 28. this limit is actually a nominal value and does not result in a fail value. cke is high during the refresh command period ( t rfc [min]), else cke is low (that is, during standby). 29. to maintain a valid level, the trans itioning edge of the input must: 29a. sustain a constant slew rate from the current ac level through to the target ac level, v il(ac) or v ih(ac) . 29b. reach at least the target ac level. 29c. after the ac target level is reached, continue to maintain at least the target dc level, v il(dc) or v ih(dc) .
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 39 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac 30. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 31. ck and ck# input slew rate must be 1 v/ns ( 2 v/ns if measured differentially). figure 13: derating data valid window ( t qh ? t dqsq) 32. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/ dm/dqs slew rate is less than 0.5 v/ns, timing must be derated: 50 ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. for -5b, -6, and -6t speed grades, the slew rate must be 0.5 v/ns. if the slew rate exceeds 4 v/ns, functionality is uncertain. 33. v dd must not vary more than 4% if cke is not active while any bank is active. 34. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 35. t hp (min) is the lesser of t cl (min) and t ch (min) actually applied to the device ck and ck# inputs, collectively, during bank active. 36. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the internal precharge command being issued. 37. any positive glitch must be less than 1/3 of the clock cycle and not more than 400mv or 2.9v (300mv or 2.9v maximum for -5b), whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either ? 300mv or 2.2v (2.4v for -5b), whichever is more positive. the average cannot be below the 2.5v (2.6v for -5b) mini- mum. 38. normal output drive curves: 38a. the full driver pull-down current va riation from min to max process; tempera- ture and voltage will lie within the oute r bounding lines of the v-i curve of figure 14 on page 40. 38b. the driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to li e within the inner bo unding lines of the v-i curve of figure 14 on page 40. 3.0ns 2.5ns 2.0ns 1.5ns 1.0ns 50/50 49/51 48/53 46/54 47/53 45/55 -6t @ t ck = 7.5ns -75e / -75 @ t ck = 7.5ns -6 @ t ck = 6ns -6t @ t ck = 6ns -5b @ t ck = 5ns 1.48 1.45 1.43 1.40 1.38 1.35 2.75 2.60 2.56 2.53 2.45 2.41 2.38 2.68 2.35 2.31 2.28 2.13 2.20 2.16 2.43 2.10 2.07 2.04 1.89 1.86 1.83 1.80 1.98 1.95 2.00 1.97 1.94 1.91 1.88 1.73 1.70 1.82 1.79 1.58 1.55 clock dut y c y cle data valid window 2.71 2.46 1.53 2.64 2.39 1.92 1.76 1.85 1.60 1.50 2.49 2.50 2.24 2.01
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 40 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac 38c. the full driver pull-up current vari ation from min to max process; temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 15 on page 40. 38d. the driver pull-up current variation within nominal limits of voltage and temper- ature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 15 on page 40. 38e. the full ratio variation of max to min pull -up and pull-down current should be between 0.71 and 1.4 for drain-to-source voltages from 0.1v to 1.0v at the same voltage and temperature. 38f. the full ratio variation of the nominal pull-up to pull-down current should be unity 10% for device drain-to-source voltages from 0.1v to 1.0v. figure 14: full drive pull-down characteristics figure 15: full drive pull-up characteristics 39. reduced output drive curves: 39a. the full driver pull-down current va riation from min to max process; tempera- ture and voltage will lie within the oute r bounding lines of the v-i curve of figure 16 on page 41. 39b. the driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to li e within the inner bo unding lines of the v-i curve of figure 16 on page 41. 39c. the full driver pull-up current vari ation from min to max process; temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 17. 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 i out (ma) v out (v) -200 -180 -160 -140 -120 -100 -8 0 -6 0 -4 0 -2 0 0 0.0 0 .5 1. 0 1 .5 2. 0 2 .5 i out (ma) v dd q - v out (v)
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 41 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac 39d. the driver pull-up current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to li e within the inner bo unding lines of the v-i curve of figure 17 on page 41. 39e. the full ratio variation of the max-to -min pull-up and pull-down current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1v to 1.0v at the same voltage and temperature. 39f. the full ratio variation of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0v. figure 16: reduced drive pull-down characteristics figure 17: reduced drive pull-up characteristics 40. the voltage levels used are derived from a minimum v dd level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will pro- vide significantly differe nt voltage values. 41. v ih overshoot: v ih,max =v dd q + 1.5v for a pulse width 3ns, and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il,min = ? 1.5v for a pulse width 3ns, and the pulse width can not be greater than 1/3 of the cycle rate. 42. v dd and v ddq must track each other. 43. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 0 10 20 30 40 50 60 70 80 0.00.51.01.5 2.0 2.5 i out (ma) v out (v) -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.5 1.0 1.5 2.0 2.5 i out (ma) v dd q - v out (v)
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 42 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac 44. t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst) or begins driving ( t rpre). 45. during initialization, v ddq , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power-up, even if v dd /v ddq are 0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. 46. the current micron part operates below 83 mhz (slowest specified jedec operating frequency). as such, future die may not reflect this option. 47. when an input signal is high or low, it is defined as a steady state logic high or low. 48. random address is changing; 50% of data is changing at every transfer. 49. random address is changing; 100% of data is changing at every transfer. 50. cke must be active (high) during the enti re time a refresh command is executed. that is, from the time the auto re fresh command is registered, cke must be active at each rising clock edge, until t rfc has been satisfied. 51. i dd2n specifies the dq, dqs, and dm to be dri ven to a valid high or low logic level. i dd2q is similar to i dd2f except i dd2q specifies the address and control inputs to remain stable. although i dd2f , i dd2n , and i dd2q are similar, i dd2f is ?worst case.? 52. whenever the operating frequency is altered, not including jitter, the dll is required to be reset followed by 200 clock cycles before any read command. 53. this is the dc voltage supplied at the dram and is inclusive of all noise up to 20 mhz. any noise above 20 mhz at the dram generated from any source other than that of the dram itself may not exceed the dc voltage range of 2.6v 100mv. 54. the -6/-6t speed grades will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency. 55. dram devices should be evenly addressed wh en being accessed. disproportionate accesses to a particular row address may result in reduction of the product lifetime.
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 43 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 28: normal output drive characteristics characteristics are specified under best, worst, and nominal process variation/ conditions voltage (v) pull-down current (ma) pull-up current (ma) nominal low nominal high min max nominal low nominal high min max 0.1 6.0 6.8 4.6 9.6 ?6.1 ?7.6 ?4.6 ?10.0 0.2 12.2 13.5 9.2 18.2 ?12.2 ?14.5 ?9.2 ?20.0 0.3 18.1 20.1 13.8 26.0 ?18.1 ?21.2 ?13.8 ?29.8 0.4 24.1 26.6 18.4 33.9 ?24.0 ?27.7 ?18.4 ?38.8 0.5 29.8 33.0 23.0 41.8 ?29.8 ?34.1 ?23.0 ?46.8 0.6 34.6 39.1 27.7 49.4 ?34.3 ?40.5 ?27.7 ?54.4 0.7 39.4 44.2 32.2 56.8 ?38.1 ?46.9 ?32.2 ?61.8 0.8 43.7 49.8 36.8 63.2 ?41.1 ?53.1 ?36.0 ?69.5 0.9 47.5 55.2 39.6 69.9 ?43.8 ?59.4 ?38.2 ?77.3 1.0 51.3 60.3 42.6 76.3 ?46.0 ?65.5 ?38.7 ?85.2 1.1 54.1 65.2 44.8 82.5 ?47.8 ?71.6 ?39.0 ?93.0 1.2 56.2 69.9 46.2 88.3 ?49.2 ?77.6 ?39.2 ?100.6 1.3 57.9 74.2 47.1 93.8 ?50.0 ?83.6 ?39.4 ?108.1 1.4 59.3 78.4 47.4 99.1 ?50.5 ?89.7 ?39.6 ?115.5 1.5 60.1 82.3 47.7 103.8 ?50.7 ?95.5 ?39.9 ?123.0 1.6 60.5 85.9 48.0 108.4 ?51.0 ?101.3 ?40.1 ?130.4 1.7 61.0 89.1 48.4 112.1 ?51.1 ?107.1 ?40.2 ?136.7 1.8 61.5 92.2 48.9 115.9 ?51.3 ?112.4 ?40.3 ?144.2 1.9 62.0 95.3 49.1 119.6 ?51.5 ?118.7 ?40.4 ?150.5 2.0 62.5 97.2 49.4 123.3 ?51.6 ?124.0 ?40.5 ?156.9 2.1 62.8 99.1 49.6 126.5 ?51.8 ?129.3 ?40.6 ?163.2 2.2 63.3 100.9 49.8 129.5 ?52.0 ?134.6 ?40.7 ?169.6 2.3 63.8 101.9 49.9 132.4 ?52.2 ?139.9 ?40.8 ?176.0 2.4 64.1 102.8 50.0 135.0 ?52.3 ?145.2 ?40.9 ?181.3 2.5 64.6 103.8 50.2 137.3 ?52.5 ?150.5 ?41.0 ?187.6 2.6 64.8 104.6 50.4 139.2 ?52.7 ?155.3 ?41.1 ?192.9 2.7 65.0 105.4 50.5 140.8 ?52.8 ?160.1 ?41.2 ?198.2
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 44 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications ? dc and ac table 29: reduced output drive characteristics characteristics are specified under best, worst, and nominal process variation/ conditions voltage (v) pull-down current (ma) pull-up current (ma) nominal low nominal high min max nominal low nominal high min max 0.1 3.4 3.8 2.6 5.0 ?3.5 ?4.3 ?2.6 ?5.0 0.2 6.9 7.6 5.2 9.9 ?6.9 ?7.8 ?5.2 ?9.9 0.3 10.3 11.4 7.8 14.6 ?10.3 ?12.0 ?7.8 ?14.6 0.4 13.6 15.1 10.4 19.2 ?13.6 ?15.7 ?10.4 ?19.2 0.5 16.9 18.7 13.0 23.6 ?16.9 ?19.3 ?13.0 ?23.6 0.6 19.9 22.1 15.7 28.0 ?19.4 ?22.9 ?15.7 ?28.0 0.7 22.3 25.0 18.2 32.2 ?21.5 ?26.5 ?18.2 ?32.2 0.8 24.7 28.2 20.8 35.8 ?23.3 ?30.1 ?20.4 ?35.8 0.9 26.9 31.3 22.4 39.5 ?24.8 ?33.6 ?21.6 ?39.5 1.0 29.0 34.1 24.1 43.2 ?26.0 ?37.1 ?21.9 ?43.2 1.1 30.6 36.9 25.4 46.7 ?27.1 ?40.3 ?22.1 ?46.7 1.2 31.8 39.5 26.2 50.0 ?27.8 ?43.1 ?22.2 ?50.0 1.3 32.8 42.0 26.6 53.1 ?28.3 ?45.8 ?22.3 ?53.1 1.4 33.5 44.4 26.8 56.1 ?28.6 ?48.4 ?22.4 ?56.1 1.5 34.0 46.6 27.0 58.7 ?28.7 ?50.7 ?22.6 ?58.7 1.6 34.3 48.6 27.2 61.4 ?28.9 ?52.9 ?22.7 ?61.4 1.7 34.5 50.5 27.4 63.5 ?28.9 ?55.0 ?22.7 ?63.5 1.8 34.8 52.2 27.7 65.6 ?29.0 ?56.8 ?22.8 ?65.6 1.9 35.1 53.9 27.8 67.7 ?29.2 ?58.7 ?22.9 ?67.7 2.0 35.4 55.0 28.0 69.8 ?29.2 ?60.0 ?22.9 ?69.8 2.1 35.6 56.1 28.1 71.6 ?29.3 ?61.2 ?23.0 ?71.6 2.2 35.8 57.1 28.2 73.3 ?29.5 ?62.4 ?23.0 ?73.3 2.3 36.1 57.7 28.3 74.9 ?29.5 ?63.1 ?23.1 ?74.9 2.4 36.3 58.2 28.3 76.4 ?29.6 ?63.8 ?23.2 ?76.4 2.5 36.5 58.7 28.4 77.7 ?29.7 ?64.4 ?23.2 ?77.7 2.6 36.7 59.2 28.5 78.8 ?29.8 ?65.1 ?23.3 ?78.8 2.7 36.8 59.6 28.6 79.7 ?29.9 ?65.8 ?23.3 ?79.7
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 45 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands commands tables 30 and 31 provide a quick reference of available commands. two additional truth tables?table 32 on page 46 and table 33 on page 47?provide current state/next state information. notes: 1. deselect and nop are functionally in terchangeable. 2. ba[1:0] provide bank address and a[ n :0] (128mb: n = 11; 256mb and 512mb: n = 12; 1gb: n = 13) provide row address. 3. ba[1:0] provide bank address; a[ i: 0] provide column address, (where a i is the most signifi- cant column address bit for a given density and configuration , see table 2 on page 2) a10 high enables the auto precharge feature (non persistent), and a10 low disables the auto precharge feature. 4. applies only to read bursts with auto precharge di sabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 5. a10 low: ba[1:0] determine which bank is precharged. a10 high: all banks are precharged and ba[1:0] are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing while in self refresh mode, all inputs and i/os are ?don?t care? except for cke. 8. ba[1:0] select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combina- tions of ba[1:0] are reserved). a[ n :0] provide the op-code to be written to the selected mode register. table 30: truth table 1 ? commands cke is high for all commands shown except self refresh; all states and se q uences not shown are illegal or reserved function cs# ras# cas# we# address notes deselect hxxx x 1 no operation (nop) lhhh x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column and start read burst) l h l h bank/col 3 write (select bank and column and start write burst) l h l l bank/col 3 burst terminate lhhl x 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) lllh x 6, 7 load mode register llllop-code8 table 31: truth table 2 ? dm operation used to mask write data, provided coincident with the corresponding data name (function) dm dq write enable l valid write inhibit h x
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 46 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands notes: 1. this table applies when cke n-1 was high and cke n is high (see table 35 on page 49) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (that is, the current state is for a specific bank and the commands shown are thos e allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: ? idle: the bank has been precharged, and t rp has been met. ? row active: a row in th e bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. ? read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. ? write: a write burst has been initiated, with auto precharge disabled , and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. com- mand inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occ urring during these st ates. allowable commands to the other bank are determined by its current st ate and table 32 and according to table 33 on page 47. ? precharging: starts with registration of a pr echarge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. ? row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. ? read with auto precharge enabled: starts with registration of a read command with auto precharge enable d and ends when t rp has been met. once t rp is met, the bank will be in the idle state. ? write with auto precharge enabled: starts with registration of a write command with auto precharge enable d and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. table 32: truth table 3 ? current state bank n ? command to bank n notes: 1?6 apply to the entire ta ble; notes appear below current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle llhh active (select and activate row) lllh auto refresh 7 llll load mode register 7 row active lhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10, 12 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10, 11 lhl l write (select column and start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8, 11
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 47 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands ? refreshing: starts with registration of an auto refresh command and ends when t rfc is met. after t rfc is met, the ddr sdram will be in the all banks idle state. ? accessing mode register: starts with registration of an lmr command and ends when t mrd has been met. after t mrd is met, the ddr sdram will be in the all banks idle state. ? precharging all: starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state. 6. all states and se q uences not shown are illegal or reserved. 7. not bank-specific; re q uires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action colu mn include reads or writes wi th auto precharge enabled and reads or writes with auto precharge disabled. 11. re q uires appropriate dm masking. 12. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. notes: 1. this table applies when cke n-1 was high and cke n is high (see table 35 on page 49) and after t xsnr has been met (if the previous state was self refresh). table 33: truth table 4 ? current state bank n ? command to bank m notes: 1?6 apply to the entire ta ble; notes appear on page 47 current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl precharge write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8 lhl l write (select column and start new write burst) 7 llhl precharge read (with auto- precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl precharge write (with auto- precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start new write burst) 7 llhl precharge
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 48 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands 2. this table describes alternate bank operation, except where noted (that is, the current state is for bank n , and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: ? idle: the bank has been precharged, and t rp has been met. ? row active: a row in th e bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. ? read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. ? write: a write burst has been initiated, with auto precharge disabled , and has not yet terminated or been terminated. ? read with auto precharge enabled: see note 3a below. ? write with auto precharge enabled: see note 3a below. a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the com- mand and ends where the precharge period (or t rp) begins. this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data tra nsfer already in process. in either case, al l other related limitation s apply (for example, contention between read data and write data must be avoided). b. the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized in table 34. 4. auto refresh and lmr commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and se q uences not shown are illegal or reserved. 7. reads or writes listed in the ?command/action? column in clude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. re q uires appropriate dm masking. 9. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. table 34: command delays cl ru = cl rounded up to the next integer from command to c o m m a n d minimum delay with concurrent auto precharge write with auto precharge read or read with auto precharge [1 + (bl/2)] t ck + t wtr write or write with auto precharge (bl/2) t ck precharge 1 t ck active 1 t ck read with auto precharge read or read with auto precharge (bl/2) t ck write or write with auto precharge [cl ru + (bl/2)] t ck precharge 1 t ck active 1 t ck
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 49 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands notes: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of com- mand n . 4. all states and se q uences not shown are illegal or reserved. 5. cke must not drop low during a column access. for a read, this means cke must stay high until after the read postamble time ( t rpst); for a write, cke must stay high until the write recovery time ( t wr) has been met. 6. once initialized, including during self refresh mode, v ref must be powered within the spec- ified range. 7. upon exit of the self refresh mode, the dll is automatically enabled. a minimum of 200 clock cycles is needed before applying a read command for the dll to lock. deselect or nop commands should be issued on any clock edges occurring during the t xsnr period. deselect the deselect function (cs# high) prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop (cs# is low with ras#, cas#, and we# are high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register (lmr) the mode registers are loaded via inputs a0?a n (see "register definition" on page 57). the lmr command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. table 35: truth table 5 ? cke notes 1?6 apply to the entire table; notes appear below cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh l h power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 7 h l all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry h h see table 30 on page 45
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 50 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands active (act) the active command is used to open (or activate) a row in a particular bank for a subsequent access, like a read or a write, as shown in figure 18. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a[ n :0] selects the row. figure 18: activating a specific row in a specific bank cs # we# c a s # ra s # c ke a dd ress row hi g h ba0, ba1 bank c k c k# don?t c are
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 51 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands read the read command is used to initiate a burst read access to an active row, as shown in figure 19 on page 51. the value on the ba 0, ba1 inputs selects the bank, and the address provided on inputs a[ i :0] (where a i is the most significant column address bit for a given density and configuration, see table 2 on page 2) selects the starting column location. figure 19: read command note: en ap = enable auto precharge; dis ap = disable auto precharge. cs # we# c a s # ra s # c ke a dd ress a10 ba0, ba1 hi g h c k c k# don t c are c ol di s ap en ap bank
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 52 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands write the write command is used to initiate a burst write access to an active row as shown in figure 20. the value on the ba0, ba1 inputs sele cts the bank, and the address provided on inputs a[ i :0] ( where a i is the most significant column add ress bit for a given density and configuration, see table 2 on page 2) sel ects the starti ng column location. figure 20: write command note: en ap = enable auto precharge; and dis ap = disable auto precharge. cs # we# c a s # ra s # c ke a10 ba0, ba1 hi g h c k c k# don t c are a dd ress c ol en ap di s ap bank
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 53 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands precharge (pre) the precharge command is used to deactivate the open row in a particular bank or the open row in all banks as shown in figure 21. the value on the ba0, ba1 inputs selects the bank, and the a10 input selects whether a single bank is precharged or whether all banks are precharged. figure 21: precharge command notes: 1. if a10 is high, bank address becomes ?don?t care.? burst terminate (bst) the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated, as sh own in ?operations? on page 54. the open page from which the read bu rst was terminated remains open. auto refresh (ar) auto refresh is used during normal operation of the ddr sdram and is analogous to cas#-before-ras# (cbr) refresh in fpm/edo drams. this command is nonpersis- tent, so it must be issued each time a refresh is required. all banks must be idle before an auto refresh command is issued. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. the self refresh command is initiated like an auto refresh command except cke is disabled (low). cs # we# c a s # ra s # c ke a10 ba0, ba1 hi g h a dd ress c k c k# don t c are bank1 all b anks one b ank
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 54 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations operations initialization prior to normal operation, ddr sdrams must be powered up and initialized in a predefined manner. operational procedures, other than those specified, may result in undefined operation. to ensure device operation, the dram must be initial ized as describe d in the following steps: 1. simultaneously apply power to v dd and v ddq . 2. apply v ref and then v tt power. v tt must be applied after v ddq to avoid device latch- up, which may cause permanent damage to the device. except for cke, inputs are not recognized as valid until after v ref is applied. 3. assert and hold cke at a lvcmos lo gic low. maintaining an lvcmos low level on cke during power-up is required to ensure that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). 4. provide stable clock signals. 5. wait at least 200s. 6. bring cke high, and provide at least one nop or deselect command. at this point, the cke input changes from a lvcmos input to a sstl_2 input only and will remain a sstl_2 input unless a power cycle occurs. 7. perform a precharge all command. 8. wait at least t rp time; during this time nops or deselect commands must be given. 9. using the lmr command, program the extended mode register (e0 = 0 to enable the dll and e1 = 0 for normal drive; or e1 = 1 for reduced drive and e2?e n must be set to 0 [where n = most significant bit]). 10. wait at least t mrd time; only nops or deselect commands are allowed. 11. using the lmr command, program the mode re gister to set operating parameters and to reset the dll. at least 200 clock cycles are required between a dll reset and any read command. 12. wait at least t mrd time; only nops or deselect commands are allowed. 13. issue a precharge all command. 14. wait at least t rp time; only nops or deselect commands are allowed. 15. issue an auto refresh command. this may be moved prior to step 13. 16. wait at least t rfc time; only nops or deselect commands are allowed. 17. issue an auto refresh command. this may be moved prior to step 13. 18. wait at least t rfc time; only nops or deselect commands are allowed. 19. although not required by the micron device, jedec requires an lmr command to clear the dll bit (set m8 = 0). if an lmr command is issued, the same operating parameters should be utilized as in step 11. 20. wait at least t mrd time; only nops or deselect commands are supported. 21. at this point the dram is ready for any valid command. at least 200 clock cycles with cke high are required between step 11 (dll reset) and any read command.
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 55 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 22: initialization flow diagram v dd an d v dd q ramp apply v ref an d v tt c ke must b e lv c mo s low apply sta b le c lo c ks brin gc ke hi g h with a nop c omman d wait at least 200s pre c har g e all assert nop or de s ele c t for t rp time c onfi g ure exten d e d mo d e re g ister c onfi g ure loa d mo d e re g ister an d reset dll assert nop or de s ele c t for t mrd time assert nop or de s ele c t for t mrd time pre c har g e all issue auto refre s h c omman d assert nop or de s ele c t for t rf c time optional lmr c omman d to c lear dll b it assert nop or de s ele c t for t mrd time dram is rea d y for any vali dc omman d step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 assert nop or de s ele c t c omman d s for t rf c issue auto refre s h c omman d assert nop or de s ele c t for t rp time
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 56 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 23: initialization timing diagram notes: 1. v tt is not applied directly to the device; however, t vtd 0 to avoid device latch-up. v ddq , v tt , and v ref v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power-up, even if v dd /v ddq are 0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. once initialized, v ref must always be powered within the specified range. 2. although not re q uired by the micron device, jedec specifies issuing another lmr command (a8 = 0) prior to activating any bank. if another lmr command is issued, the same, previ- ously issued operating parameters must be used. 3. the two auto refresh commands at td0 and te0 may be applied following the lmr com- mand at ta0. 4. t mrd is re q uired before any command can be ap plied (during mr d time only nops or deselects are allowed), and 200 cycles of ck are re q uired before a read command can be issued. 5. while programming the operating parameters, reset the dll with a8 = 1. t vtd 1 cke lvcmos low level dq ba0, ba1 200 cycles of ck4 load extended mode register load mode register5 t mrd t mrd t rp t rfc t rfc t is power-up: v dd and ck stable t = 200s high-z t ih dm dqs high-z address ra a10 all banks ck ck# t ch t cl t ck v tt 1 v ref v dd v dd q command lmr nop pre lmr ar ar act 2 t is t ih ba0 = 1 ba1 = 0 t is t ih t is t ih ba0 = 0 ba1 = 0 t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code code t is t ih code code 3 pre all banks t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 ( ) ( ) don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ra indicates a break in time scale
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 57 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations register definition mode register the mode register is used to define the speci fic ddr sdram mode of operation. this definition includes the selec tion of a burst length, a burst type, a cas latency, and an operating mode, as shown in figure 24. the mode register is programmed via the lmr command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or until the device loses power (except for bit a8, which is self- clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. mode register bits a[2:0] specify the burst length, a3 specifies the type of burst (sequen- tial or interleaved), a[6:4] specify the cas latency, and a[ n :7] specify the operating mode. figure 24: mode register definition notes: 1. n is the most significant row address bit from table 2 on page 2. burst type se q uential interleaved cas latency reserved reserved 2 3 (-5b only) reserved reserved 2.5 reserved burst length cas latency bt 0 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 m3 0 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 operating mode . . . a n ba0 ba1 . . . n 1 n + 1 0 n + 2 operating mode normal operation normal operation/reset dll all other states reserved m8 0 1 ? m9 0 0 ? . . . 0 0 ? m n 0 0 ? m7 0 0 ? m6?m0 valid valid ? burst length reserved 2 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m n + 1 0 1 0 1 mode register definition base mode register extended mode register reserved reserved m n + 2 0 0 1 1
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 58 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations burst length (bl) read and write accesses to the ddr sdram ar e burst oriented, with the burst length being programmable for both read and write bursts, as shown in figure 24 on page 57. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. bl = 2, bl = 4, or bl = 8 locations are available for both the sequential and the in terleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued , a block of columns equal to the burst length is effectively selected. all acce sses for that burst take place within this block? meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a[ i :1] when bl = 2, by a[ i :2] when bl = 4, and by a[ i :3] when bl = 8 (where a i is the most significant column addre ss bit for a given configuration). the remaining (least signifi cant) address bit(s) is (are) used to select the starting location within the block. for example: for bl = 8, a[ i :3]select the eight-da ta-element block; a[2:0] select the first access within the block. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as th e burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in table 36. table 36: burst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2?? a0 ?? ??0 0-1 0-1 ??1 1-0 1-0 4? a1 a0 ?? ? 0 0 0-1-2-3 0-1-2-3 ? 0 1 1-2-3-0 1-0-3-2 ? 1 0 2-3-0-1 2-3-0-1 ? 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 ?? 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 59 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations cas latency (cl) the cl is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2, 2.5, or 3 (-5b only) clocks, as shown in figure 25. reserved states should not be used, as unknown operation or incompatibility with future versions may result. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . table 37 on page 60 indi- cates the operating frequencies at which each cl setting can be used. figure 25: cas latency note: bl = 4 in the cases shown; shown with nominal t ac, t dqsck, and t dqsq. c k c k# c omman d dq dq s c l = 2 read nop nop nop read nop nop nop c k c k# c omman d dq dq s c l = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don t c are transitionin g data read nop nop nop c k c k# c omman d dq dq s c l = 3 t0 t1 t2 t3 t3n
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 60 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations operating mode the normal operating mode is selected by iss uing an lmr command with bits a7?a n each set to zero and bits a[6:0] set to the desired values. a dll reset is initiated by issuing an lmr command with bits a7 and a[ n :9] each set to zero, bit a8 set to one, and bits a[6:0] set to the desired values. although not required by the micron device, jedec specifications recommend that an lmr command resetting the dll should always be followed by an lmr command selecting normal operating mode. all other combinations of values for a[ n :7] are reserved for future use and/or test modes. test modes and reserved states should not be used, as unknown operation or incompat- ibility with future versions may result. extended mode register the extended mode register controls functions be yond those controlled by the mode register; these additi onal functions are dll enable/disable and output drive strength. these functions are controlled via the bits sho wn in figure 26 on page 61. the extended mode register is programmed via the lmr command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is prog rammed again or until the device loses power. the enabling of th e dll should always be followed by an lmr command to the mode register (ba0/ba1 = 0) to reset the dll. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time be fore initiating any subsequent operation. violating either requirement coul d result in an unspe cified operation. output drive strength the normal drive strength for all outputs is sp ecified to be sstl_2, class ii. this option is intended for the support of the lighter load and/or point-to-poi nt environments. the selection of the reduced drive strength will alter the dq and dqs pins from sstl_2, class ii drive strength to a reduced drive st rength, which is approxi mately 54% of the sstl_2, class ii drive strength. dll enable/disable when the part is running without the dll enabled, device functional ity may be altered. the dll must be enabled for normal operation. dll enable is required during power- up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation (when the de vice exits self refresh mode, the dll is enabled automatically). anytime the dll is enabled, 200 clock cycles with cke high must occur before a read command can be issued. table 37: cas latency speed allowable operating clock frequency (mhz) cl = 2 cl = 2.5 cl = 3 -5b 75 f 133 75 f 167 133 f 200 -6/-6t 75 f 133 75 f 167 ? -75e 75 f 133 75 f 133 ? -75z 75 f 133 75 f 133 ? -75 75 f 100 75 f 133 ?
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 61 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 26: extended mode register definition notes: 1. n is the most significant row address bit from table 2 on page 2. 2. the qfc# option is not supported. active after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 133 mhz clock (7.5ns period) results in 2.7 clocks rounded to 3. this is reflected in figure 27 on page 62, which covers any case where 2 < t rcd (min)/ t ck 3 (figure 27 also shows the same case for t rrd; the same procedure is used to convert other specification limits fr om time units to clock cycles). a row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. a subsequent active command to a different row in the same bank can only be issued after the previous active ro w has been ?closed? (pre charged). the minimum time interval between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd. operating mode reserved reserved e3 0 ? e4 0 ? e1, e0 valid ? dll enable disable a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 821 0 1 e0 0 1 drive strength normal reduced e1 operating mode . . . a n ba1 ba0 . . . n 1 n + 1 n + 2 e6 0 ? e7 0 ? e8 0 ? e9 0 ? e5 0 ? . . . 0 ? e n 0 ? ds e2 2 0 ? m n + 1 0 1 0 1 mode register definition base mode register extended mode register reserved reserved m n + 2 0 0 1 1 dll 0 1 0
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 62 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 27: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min/ t ck 3 read during the read command, the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. note: for the read commands used in the follo wing illustrations, auto precharge is dis- abled. during read bursts, the valid data-out element from the starting column address will be available following the cl after the read command. each subsequent data-out element will be valid nominally at the next posi tive or negative clock edge (that is, at the next crossing of ck and ck#). figure 28 on page 64 shows the general ti ming for each possible cl setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other command s have been initiated, the dq will go high-z. detailed explanations of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid da ta window are de picted in figure 36 on page 72 and figure 37 on page 73. detailed explanations of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) are depicted in figure 38 on page 74. data from any read burst may be concatenated or truncated with data from a subse- quent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst foll ows either the last element of a completed burst or the last desired data element of a long er burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 29 on page 65. a read command can be initiated on any clock cycle following a prev ious read command. nonconse cutive read data is illustrated in figure 30 on page 66. full-speed random read accesses within a page (or pages) can be performed, as shown in figure 31 on page 67. c omman d ba0, ba1 a c ta c t nop t rrd t r c d c k c k# bank x bank y a dd ress row row nop rd/wr nop bank y c ol nop t0 t1 t2 t3 t4 t5 t 6 t7 don t c are nop
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 63 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations data from any read burst may be truncated with a burst terminate command, as shown in figure 32 on page 68. the burst terminate latency is equal to the cl, that is, the burst terminate command should be issued x cycles after the read command where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 33 on page 69. the t dqss (nom) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the section on writes.) a read burst may be followed by, or truncated with, a precharge command to the same bank provided that auto precharge was not acti- vated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 34 on page 70. following the precharge command, a subsequent command to the same bank cannot be issued until both t ras and t rp have been met. part of the row precharge time is hidden during the access of the last data elements.
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 64 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 28: read burst notes: 1. do n = data-out from column n . 2. bl = 4. 3. three subse q uent elements of data-out appear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. read nop nop nop nop nop read nop nop nop nop nop cl = 2 cl = 2.5 do n do n t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 read nop nop nop nop nop cl = 3 do n t0 t1 t2 t3 t4n t3n t4 t5 bank a , col n bank a , col n bank a , col n command address dqs dq ck# ck command address dqs dq ck# ck command address dqs dq ck# ck transitioning data don?t care
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 65 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 29: consecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4 or bl = 8 (if bl = 4, the bursts are concatenated; if bl = 8, the second burst interrupts the first). 3. three subse q uent elements of data-out appear in the programmed order following do n. 4. three (or seven) subse q uent elements of data-out appear in the programmed order follow- ing do b. 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read commands are issued to same device. read nop read nop nop nop read nop read nop nop nop cl = 2 cl = 2.5 do n do b do n do b t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n read nop read nop nop nop cl = 3 do n do b t0 t1 t2 t3 t3n t4 t5 t4n t5n bank, col n bank, col b bank, col n bank, col b bank, col n bank, col b command address dqs dq ck# ck command address dqs dq ck# ck command address dqs dq ck# ck transitioning data don?t care
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 66 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 30: nonconsecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4 or bl = 8 (if bl = 4, the bursts are concatenated; if bl = 8, the second burst interrupts the first). 3. three subse q uent elements of data-out appear in the programmed order following do n . 4. three (or seven) subse q uent elements of data-out appear in the programmed order follow- ing do b . 5. shown with nominal t ac, t dqsck, and t dqsq. read nop nop nop nop nop read c l = 2 c l = 2.5 do n t0 t1 t2 t3 t2n t3n t4 t5 t5n t 6 read nop nop nop nop nop read t0 t1 t2 t3 t2n t3n t4 t5 t5n t 6 do b do n do b c l = 3 read nop nop nop nop nop read t0 t1 t2 t3 t3n t4 t5 t 6 do n do b t4n bank, c ol n bank, c ol b bank, c ol n bank, c ol b bank, c ol n bank, c ol b c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k transitionin g data don t c are
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 67 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 31: random read accesses notes: 1. do n (or x or b or g ) = data-out from column n (or column x or column b or column g ). 2. bl = 2, bl = 4, or bl = 8 (if bl = 4 or bl = 8, the following burst interrupts the previous). 3. n ', x ', b ', or g ' indicate the next data-out following do n , do x , do b , or do g , respectively . 4. reads are to an active row in any bank . 5. shown with nominal t ac, t dqsck, and t dqsq. read read read nop nop read c l = 2 c l = 2.5 do n do x' do g do n' do b do x do b' do n do x' do n' do b do x do b' t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n read read read nop nop read t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n c l = 3 do n do x' do n' do b do x do b' read read read nop nop read t0 t1 t2 t3 t3n t4 t5 t4n t5n bank, c ol n bank, c ol b bank, c ol x bank, c ol g bank, c ol n bank, c ol b bank, c ol x bank, c ol g bank, c ol n bank, c ol b bank, c ol x bank, c ol g c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k transitionin g data don t c are
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 68 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 32: terminating a read burst notes: 1. page remains open. 2. do n = data-out from column n . 3. bl = 4. 4. subse q uent element of data-out appears in the programmed order following do n . 5. shown with nominal t ac, t dqsck, and t dqsq. read nop nop nop nop bank a , col n read nop nop nop nop bank a , col n cl = 2 cl = 2.5 do n do n t0 t1 t2 t3 t2n t4 t5 t0 t1 t2 t3 t2n t4 t5 read nop nop nop nop bank a , col n cl = 3 do n t0 t1 t2 t3 t3n t4 t5 bst 1 bst 1 bst 1 command address dqs dq ck# ck command address dqs dq ck# ck command address dqs dq ck# ck transitioning data don?t care
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 69 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 33: read-to-write notes: 1. page remains open. 2. do n = data-out from column n ; di b = data-in from column b . 3. bl = 4 (applies for bursts of 8 as well; if bl = 2, the burst command shown can be nop). 4. one subse q uent element of data-out appears in the programmed order following do n. 5. data-in elements are applied following di b in the programmed order . 6. shown with nominal t ac, t dqsck, and t dqsq. read b s t 1 nop nop nop bank, c ol n write bank, c ol b t0 t1 t2 t3 t2n t4 t5 t4n t5n t (nom) dq ss di b read b s t 1 nop write nop bank a, c ol n nop t0 t1 t2 t3 t3n t4 t5 t5n do n do n t (nom) dq ss read nop nop bank, c ol n write bank, c ol b t0 t1 t2 t3 t2n t4 t5 t5n t (nom) dq ss di b do n nop c l = 2.5 c l = 2 t3n c l = 3 di b b s t 1 c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k transitionin g data don t c are dm dm dm
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 70 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 34: read-to-precharge notes: 1. provided t ras (min) is met, a read command with auto precharge enabled would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl/2. 2. do n = data-out from column n . 3. bl = 4 or an interrupted burst of 8. 4. three subse q uent elements of data-out appear in the programmed order following do n . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. read-to-precharge e q uals two clocks, which allows two data pairs of data -out; it is also assumed that t ras (min) is met. 7. an active command to the same bank is only allowed if t rc (min) is met. read nop pre nop nop a c t bank a , c ol n bank a , ( a or all ) bank a , row read nop pre nop nop a c t bank a , c ol n c l = 2 t rp t rp c l = 2.5 do n do n t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 bank a , ( a or all ) bank a , row read nop pre nop nop a c t bank a , c ol n t rp c l = 3 do n t0 t1 t2 t3 t4n t3n t4 t5 bank a , ( a or all ) bank a , row c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k c omman d a dd ress dq s dq c k# c k transitionin g data don t c are
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 71 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 35: bank read ? without auto precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4. 3. the precharge command can only be applied at t5 if t ras (min) is met. 4. disable auto precharge. 5. ?don?t care? if a10 is high at t5. 6. do n (or b ) = data-out from column n (or column b ); subse q uent elements are provided in the programmed order. 7. refer to figure 36 on page 72, figure 37 on page 73, and figure 38 on page 74 for detailed dqs and dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih t rcd t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dqs case 1: t ac ( min) and t dqsck ( min) case 2: t ac ( max) and t dqsck ( max) dqs t rpre t rpre t rpst t rpst t dqsck ( min) t lz ( min) t ac ( min) t lz ( min) do n t hz ( max) t ac ( max) do n act col n bank x bank x act bank x t dqsck (max) nop 1 nop 1 nop 1 nop 1 nop 1 read 2 pre 3 4 bank x 5 t ras 3 row row row row dq dq command address transitioning data don?t care all banks one bank
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 72 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 36: x4, x8 data output timing ? t dqsq, t qh, and data valid window notes: 1. t hp is the lesser of t cl or t ch clock transition co llectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulati ve over time, begins with dqs transition, and en ds with the last valid dq transition. 3. dq transitioning after dqs transition define the t dqsq window. dqs transitions at t2 and t2n are an ?early dqs?; at t3, a ?nominal dqs?; and at t3n, a ?late dqs?. 4. for a x4, only two dq apply. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for eac h dqs transitions and is defined as t qh - t dqsq. dq (last d ata vali d ) dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq s 3 dq (last d ata vali d ) dq (first d ata no lon g er vali d ) dq (first d ata no lon g er vali d ) all dq an d dq sc olle c tively 6 earliest si g nal transition latest si g nal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n c k c k# t1 t2 t3 t4 t2n t3n t qh 5 t hp 1 t hp 1 t hp 1 t qh 5 t qh 5 t hp 1 t hp 1 t hp 1 t qh 5 t dq s q 2 t dq s q 2 t dq s q 2 t dq s q 2 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 73 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 37: x16 data output timing ? t dqsq, t qh, and data valid window notes: 1. t hp is the lesser of t cl or t ch clock transition co llectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulati ve over time, begins with dqs transition, and en ds with the last valid dq transition. 3. dq transitioning after dqs transition define the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 4. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for each dqs transition and is t qh - t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. dq (last d ata vali d ) 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 ldq s 3 dq (last d ata vali d ) 4 dq (first d ata no lon g er vali d ) 4 dq (first d ata no lon g er vali d ) 4 dq0?dq7 an d ldq sc olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n c k c k# t1 t2 t3 t4 t2n t3n t qh 5 t qh 5 t dq s q 2 t dq s q 2 t dq s q 2 t dq s q 2 data vali d win d ow data vali d win d ow dq (last d ata vali d ) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udq s 3 dq (last d ata vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq8?dq15 an d udq sc olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 5 t qh 5 t qh 5 t qh 5 t dq s q 2 t dq s q 2 t dq s q 2 t dq s q 2 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t qh 5 t qh 5 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow upper b yte lower b yte data vali d win d ow
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 74 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 38: data output timing ? t ac and t dqsck notes: 1. read command with cl = 2 issued at t0. 2. t dqsck is the dqs output window relative to ck and is the ?long term? component of the dqs skew. 3. dq transitioning after dqs transition define the t dqsq window. 4. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 5. t ac is the dq output window relative to ck and is the ?long term? component of dq skew. 6. t lz (min) and t ac (min) are the first valid signal transitions. 7. t hz (max) and t ac (max) are the latest valid signal transitions. write during a write command, the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst (after t wr time); if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing co incident with the data. if a given dm signal is registered low, the corresponding data will be written to memory. if the dm signal is registered high, the corresponding data inputs will be igno red, and a write will not be executed to that byte/column location. note: for the write commands used in the following illustrations, auto precharge is dis- abled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data eleme nts will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (from 75% to 125% of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases (that is, t dqss [min] and t dqss [max]) might not be intuitive; they have also been included. figure 39 on page 76 shows th e nominal case and the extremes of t dqss for bl = 4. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. ck ck# dqs or ldqs/udqs 3 t1 t2 t3 t4 t5 t2n t3n t4n t5n t6 t rpst t lz (min) t dqsck 2 (max) t dqsck 2 (min) t dqsck 2 (max) t dqsck 2 (min) t hz (max) all dq values collectively 4 t ac 5 (min) t ac 5 (max) t lz (min) t hz (max) t2 t2 t2n t3n t4n t5n t2n t2n t3n t3n t4n t4n t5n t5n t3 t4 t4 t5 t5 t2 t3 t4 t5 t3 dq (last data valid) dq (first data valid) t0 1 t rpre
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 75 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any posi tive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of des ired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 40 on page 77 shows concatenated bursts of 4. an example of nonconsecutive writes is shown in figure 41 on page 78. full-speed random wr ite accesses within a page or pages can be performed as shown in figure 42 on page 78. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be met, as shown in figure 43 on page 79. data for any write burst may be truncated by a subsequent read command, as shown in figure 44 on page 80. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 45 on page 81. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met, as shown in figure 46 on page 82. data for any write burst may be truncated by a subsequent precharge command, as shown in figure 47 on page 83 and figure 48 on page 84. only the data-in pairs regis- tered prior to the t wr period are written to the internal array; any subsequent data-in should be masked with dm, as shown in figures 47 and 48. after the precharge command, a subsequent command to the same bank cannot be issued until t rp is met.
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 76 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 39: write burst notes: 1. di b = data-in for column b . 2. three subse q uent elements of data-in are applied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. a10 is low with the write command (auto precharge is disabled). dqs t dqss (max) t dqss (nom) t dqss (min) t dqss dm dq ck ck# command write nop nop address bank a , col b nop t0 t1 t2 t3 t2n dqs t dqss dm dq dqs dm dq di b di b di b don?t care transitioning data t dqss
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 77 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 40: consecutive write-to-write notes: 1. di b (or n ) = data-in from column b (or column n ). 2. three subse q uent elements of data-in are applied in the programmed order following di b . 3. three subse q uent elements of data-in are applied in the programmed order following di n . 4. an uninterrupted burst of 4 is shown. 5. each write command may be to any bank. address t dqss (nom) ck ck# command write nop write nop nop bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t1n dq dqs dm di n di b don?t care transitioning data t dqss
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 78 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 41: nonconsecutive write-to-write notes: 1. di b (or n ) = data-in from column b (or column n ). 2. three subse q uent elements of data-in are applied in the programmed order following di b . 3. three subse q uent elements of data-in are applied in the programmed order following di n . 4. an uninterrupted burst of 4 is shown . 5. each write command may be to any bank. figure 42: random write cycles notes: 1. di b (or x or n or a or g ) = data-in from column b (or column x , or column n , or column a ,or column g ). 2. b ' , x ' , n ' , a ' or g ' indicate the next data-in following do b , do x , do n ,do a , or do g , respectively. 3. programmed bl = 2, bl = 4, or bl = 8 in cases shown. 4. each write command may be to any bank. ck command write nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t1n t5n dq dqs dm di n di b t dqss (nom) t dqss don?t care transitioning data ck# t dqss (nom) ck ck# command write write write write nop address bank, col b bank, col x bank, col n bank, col g write bank, col a t0 t1 t2 t3 t2n t4 t5 t4n t1n t3n t5n dq dqs dm di b di b ' di x di x ' di n di n ' di a di a ' di g di g ' don?t care transitioning data
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 79 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 43: write-to-read ? uninterrupting notes: 1. di b = data-in for column b ; do n = data-out for column n . 2. three subse q uent elements of data-in are applied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. the read and write commands are to the same device. however, the read and write commands may be to different devices, in which case t wtr is not re q uired, and the read command could be applied earlier. 6. a10 is low with the write command (auto precharge is disabled). t dqss (nom) ck ck# command write nop nop read nop nop address bank a , col b bank a , col n nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t6n t wtr cl = 2 dq dqs dm di b do n t dqss t dqss (min) cl = 2 dq dqs dm di b do n t dqss t dqss (max) cl = 2 dq dqs dm di b do n t dqss don?t care transitioning data
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 80 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 44: write-to-read ? interrupting notes: 1. di b = data-in for column b ; do n = data-out for column n . 2. an interrupted burst of 4 is shown; two data elements are written. 3. one subse q uent element of data-in is applied in the programmed order following di b . 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. a10 is low with the write command (auto precharge is disabled). 6. dqs is re q uired at t2 and t2n (nominal case) to register dm. 7. if the burst of 8 is used, dm and dqs are re q uired at t3 and t3n because the read com- mand will not mask these two data elements. t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t6 t6n t wtr cl = 2 dq dqs dm di b do n t dqss (min) cl = 2 dq dqs dm di b t dqss (max) cl = 2 dq dqs dm di b do n do n don?t care transitioning data t dqss t dqss t dqss t3n
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 81 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 45: write-to-read ? odd number of data, interrupting notes: 1. di b = data-in for column b ; do n = data-out for column n . 2. an interrupted burst of 4 is shown; one data element is written. 3. t wtr is referenced from the first positive ck edge after the last desired data-in pair (not the last two data elements). 4. a10 is low with the write command (auto precharge is disabled). 5. dqs is re q uired at t1n, t2, and t2n (nominal case) to register dm. 6. if the burst of 8 is used, dm and dqs are re q uired at t3?t3n because the read command will not mask these data elements. t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t1n t6 t6n t5n t wtr cl = 2 dq dqs dm di b do n t dqss (min) cl = 2 dq dqs dm di b do n t dqss (max) cl = 2 dq dqs dm di b do n don?t care transitioning data t dqss t dqss t dqss t3n
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 82 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 46: write-to-precharge ? uninterrupting notes: 1. di b = data-in for column b . 2. three subse q uent elements of data-in are applied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. the precharge and write commands are to the same device. however, the precharge and write commands may be to different devices, in which case t wr is not re q uired, and the precharge command could be applied earlier. 6. a10 is low with the write command (auto precharge is disabled). t dqss (nom) ck ck# command write nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t wr t rp dq dqs dm di b t dqss (min) dq dqs dm di b t dqss (max) dq dqs dm di b don?t care transitioning data t dqss t dqss t dqss pre
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 83 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 47: write-to-precharge ? interrupting notes: 1. di b = data-in for column b . 2. subse q uent element of data-in is applied in the programmed order following di b . 3. an interrupted burst of 8 is shown; two data elements are written. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. a10 is low with the write command (auto precharge is disabled). 6. dqs is re q uired at t4 and t4n (nominal case) to register dm. 7. if the burst of 4 is used, dqs and dm are not re q uired at t3, t3n, t4, and t4n. t dqss t dqss (nom) ck ck# command write nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t wr t rp dq dqs dm di b t dqss t dqss (min) dq dqs dm di b t dqss t dqss (max) dq dqs dm di b don?t care transitioning data t3n t4n pre
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 84 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 48: write-to-precharge ? odd number of data, interrupting notes: 1. di b = data-in for column b . 2. an interrupted burst of 8 is shown; one data element is written. 3. t wr is referenced from the first positive ck edge after the last data-in pair. 4. a10 is low with the write command (auto precharge is disabled). 5. dqs is re q uired at t4 and t4n (nominal case) to register dm. 6. if the burst of 4 is used, dqs and dm are not re q uired at t3, t3n, t4, and t4n. t dqss t dqss (nom) ck ck# command write nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t wr t rp dq dqs dm di b t dqss t dqss (min) dq dqs dm t dqss t dqss (max) dq dqs dm di b di b don?t care transitioning data t3n t4n pre
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 85 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 49: bank write ? without auto precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t8. 5. di b = data-in from column b ; subse q uent elements are provided in the programmed order. 6. see figure 51 on page 87 for detailed dq timing. command nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 write 2 3 bank x 4 dq 5 address row row ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n act col n one bank all banks bank x pre bank x t dqsl t dqsh t wpst dqs dm di b t ds t dh t dqss (nom) t wpre t wpres don?t care transitioning data
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 86 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 50: write ? dm operation notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t8. 5. di b = data-in from column b ; subse q uent elements are provided in the programmed order. 6. see figure 51 on page 87 for detailed dq timing. command nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 3 bank x 4 dq 5 write 2 address row row ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n act col n one bank all banks bank x pre bank x t dqsl t dqsh t wpst dqs dm di b t ds t dh don?t care transitioning data t dqss (nom) t wpres t wpre
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 87 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 51: data input timing notes: 1. write command issued at t0. 2. t dsh (min) generally occurs during t dqss (min). 3. t dss (min) generally occurs during t dqss (max). 4. for x16, ldqs controls the lower byte and udqs controls the upper byte. 5. di b = data-in from column b . precharge the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued, except in the case of concurrent auto precharge. with concurrent auto precharge, a read or write co mmand to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks ar e to be precharged, ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge func- tion described above, but wit hout requiring an explicit comm and. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is either enabled or disabled for each individual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. this ?earliest valid stage? is determined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min), as described for each burst type in ?operations? on page 54. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. t0 1 t dsh 2 t dsh 2 t dss 3 t dss 3 di b dqs t dqss t dqsh t wpst t dh t ds t dqsl dm dq ck ck# t1 t1n t2 t2n t3 don?t care transitioning data t wpre t wpres
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 88 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 52: bank read ? with auto precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4. 3. the read command can only be applied at t3 if t rap is satisfied at t3. 4. enable auto precharge. 5. t rp starts only after t ras has been satisfied. 6. do n = data-out from column n; subse q uent elements are provided in the programmed order. 7. refer to figure 36 on page 72, figure 37 on page 73, and figure 38 on page 74 for detailed dqs and dq timing. nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 read 2,3 4 t r c d, t rap 3 dq 6 dq 6 c omman d t rp 5 a dd ress t lz (min) row row row row c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih i s ih t r c c l = 2 dm t0 t1 t2 t3 t4 t5 t5n t 6 n t 6 t7 t8 dq s c ase 1: t a c (min) an d t dq sc k (min) c ase 2: t a c ( max) an d t dq sc k ( max) dq s t rpre t rpre t rp s t t dq sc k ( min) t dq sc k ( max) t a c ( min) t lz ( min) do n t hz ( max) t a c ( max) do n a c t c ol n bank x bank x a c t bank x t ra s don t c are transitionin g data t rp s t
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 89 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 53: bank write ? with auto precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4. 3. enable auto precharge. 4. di n = data-out from column n ; subse q uent elements are provided in the programmed order. 5. see figure 51 on page 87 for detailed dq timing. auto refresh during auto refresh, the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the ddr sdram requires auto refresh cycles at an average interval of t refi (max). to allow for improved effi ciency in scheduling and switching between tasks, some flexi- bility in the absolute refresh interval is prov ided. a maximum of eight auto refresh commands can be posted to any given dd r sdram, meaning that the maximum abso- lute interval between any auto refresh command and the next auto refresh command is 9 t refi(= t refc). jedec specifications only support 8 t refi; micron specifications exceed the jedec requirement by one clock. this maximum absolute interval is to allow future support for dll updates, internal to the ddr sdram, to be restricted to auto refresh cycles, without allowing excessive drift in t ac between updates. command nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 write 2 3 dq 4 address row row ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n act col n bank x bank x t dqsl t dqsh t wpst dqs dm di b t ds t dh t dqss (nom) don?t care transitioning data t wpres t wpre
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 90 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations although not a jedec requirement, to provid e for future functionality features, cke must be active (high) during the auto refresh period. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. figure 54: auto refresh mode notes: 1. nop commands are shown for ease of illustration; other valid commands may be possible at these times. cke must be active during clock-posi tive tran sitions. 2. nop or command inhibit are the only commands allowed until after t rfc time; cke must be active duri ng clock-positive transitions. 3. the second auto refresh is not re q uired and is only shown as an example of two back-to- back auto refresh commands. 4. ?don?t care? if a10 is high at this point; a10 must be high if more than one bank is active (that is, must precharge all active banks). 5. dm, dq, and dqs signals are all ?don?t care?/high-z for the operations shown. self refresh when in the self refresh mode, the ddr sdram retains data without external clocking. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (a dll reset and 200 clock cycles must then occur before a read command can be issued). input signals except cke are ?don?t care? during self refresh. v ref voltage is also requir ed for the full duration of self refresh. the procedure for exiting sel f refresh requires a sequence of commands. first, ck and ck# must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for t xsrd time, then a dll reset (via c k c k# c omman d nop 1 vali d vali d nop 1 nop 1 pre c ke ra a dd ress a10 ba0, ba1 bank(s) 4 ba ar nop 1,2 ar 3 nop 1,2 a c t nop 1 one b ank all b anks c k t c h t c l t i s t i s t ih t ih t i s t ih ra dq 5 dm 5 dq s 5 t rf c t rp t rf c t0 t1 t2 t3 t4 ta0 t b 0 ta1 t b 1t b 2 don t c are ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 91 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations the extended mode register) and nops for 200 ad ditional clock cycles before applying a read. any command other than a read can be performed t xsnr (min) after the dll reset. nop or deselect commands must be issued during the t xsnr (min) time. figure 55: self refresh mode notes: 1. clock must be stable until after the self refresh command has been registered. a change in clock fre q uency is allowed before ta0, provided it is within the specified t ck limits. regardless, the clock must be stable before exiting self refresh mode?that is, the clock must be cycling within specifications by ta0. 2. nops are interchangeable with deselect commands. 3. auto refresh is not re q uired at this point but is highly recommended. 4. device must be in the all banks idle sta te prior to entering self refresh mode. 5. t xsnr is re q uired before any non-read command can be applied; that is only nop or dese- lect commands are allowed until tb1. 6. t xsrd (200 cycles of a valid clock with cke = high) is re q uired before any read command can be applied. 7. as a general rule, any time self refresh mode is exited, the dram ma y not re-enter the self refresh mode until all rows have been refreshed via the auto refresh command at the distributed refresh rate, t refi, or faster. however, the self refresh mode may be re-entered anytime after exiting if each of the following conditions is met: 7a. the dram had been in the self refresh mode for a minimum of 200ms prior to exiting. 7b. t xsnr and t xsrd are not violated. 7c. at least two auto refresh comma nds are performed during each t refi interval while the dram remains out of self refresh mode. 8. if the clock fre q uency is changed during self re fresh mode, a dll reset is re q uired upon exit. 9. once the device is initialized, v ref must always be powered within specified range. c k 1 c k# c omman d 2 nop ar a dd ress c ke dq dm dq s nop t rp 4 t c h t c l t c k t i s t i s t ih t i s t ih t i s enter self refresh mo d e 7 exit self refresh mo d e 7 t0 t1 1 ta1 don t c are ta0 1 t x s rd 6 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop vali d 3 vali d ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t x s nr 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ta2 t b 1t b 2t c 1 vali d vali d vali d t i s t ih ( ) ( ) ( ) ( ) vali d ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 92 ?2000 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations power-down (cke not active) unlike sdr sdrams, ddr sdrams require cke to be active at all times an access is in progress, from the issuing of a read or write command, until completion of the access. thus a clock suspend is not supported. for reads , an access completion is defined when the read postamble is satisfied; for writes, when the write recovery time ( t wr) is satisfied. power-down, as shown in figure 56 on page 93, is entered when cke is registered low and all criteria in table 35 on page 49 are met. if power-down occurs when all banks are idle, this mode is referred to as prec harge power-down; if power-down occurs when a row is active in any bank, this mode is re ferred to as active power-down. entering power- down deactivates the input and output buffers, excluding ck, ck#, and cke. for maximum power savings, the dll is frozen during precharge power-down mode. exiting power-down requires the device to be at the same voltage and fr equency as when it entered power-down. however, power-down duration is limited by the refresh require- ments of the device ( t refc). while in power-down, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, while all other input signals are ?don?t care.? the power- down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). a valid exec utable command may be applied one clock cycle later.
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc.all other trademarks are the property of their respective o wners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 512mb: x4, x8, x16 ddr sdram operations pdf: 09005aef80768abb/source: 09005aef82a95a3a micron technology, inc., reserves the right to change products or specifications without notice. ddr_x4x8x16_core2.fm - 512mb ddr: rev. q; core ddr rev. e 7/11 en 93 ?2000 micron technology, inc. all rights reserved. figure 56: power-down mode notes: 1. once initialized, v ref must always be powered within the specified range. 2. if this command is a precharge (or if the de vice is already in the idle state), then the power-down mode shown is pr echarge power-down. if th is command is an active (or if at least one row is already active), then the power -down mode shown is active power-down. 3. no column accesses are allowed to be in progress at the time power-down is entered. c k c k# c omman d vali d 2 nop a dd ress c ke dq dm dq s vali d t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t i s enter 3 power- d own mo d e exit power- d own mo d e t ref c ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t 0 t1 ta 0 ta1 ta 2 t 2 nop don t c are ( ) ( ) ( ) ( ) vali d vali d 1

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